3D Memory Sub-Block Segmentation for Erase Control
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Solution Overview
Problem
The increasing stacked height of semiconductor memory devices with three-dimensional arrays leads to a reduction in the number of memory blocks, limiting the number of replaceable blocks in case of failures and reducing productivity due to the need for erase operations in units of larger memory blocks.
Innovation Solution
A nonvolatile memory device with a three-dimensional memory cell array that includes sub-blocks, allowing for independent erase operations by applying specific voltages to selected well regions, enabling more precise control and reducing the risk of unintentional erase or program operations in unselected blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the stacked height of three-dimensional memory devices is increased to improve integration density, then the number of memory cells per block increases, but the number of memory blocks decreases, limiting replaceability and reducing productivity
Solution Approach 1:
The memory block is segmented into multiple sub-blocks, each with its own independent well region. This allows selective erase operations on individual sub-blocks rather than requiring erasure of the entire block, thereby maintaining productivity despite increased integration density through higher stacked height.
2Quantity of substance
If the stacked height of three-dimensional memory devices is increased to improve integration density, then the number of memory cells per block increases, but the number of replaceable blocks decreases
Solution Approach 1:
By dividing each memory block into multiple sub-blocks with independent well regions, the patent enables selective replacement or repair of individual sub-blocks. This segmentation maintains adaptability and replaceability even as integration density increases through greater stacked height.
3Device complexity
If erase operations are performed in units of entire memory blocks, then the structure is simpler, but it causes unintentional erase or program operations in unselected blocks and reduces efficiency
Solution Approach 1:
The patent segments the memory block into sub-blocks with independent well regions, enabling targeted erase operations on selected sub-blocks only. This segmentation prevents unintentional erasure of unselected blocks while maintaining operational efficiency, balancing structural complexity with productivity.
Solution Approach 2:
The patent applies different voltages to different well regions corresponding to selected and unselected sub-blocks. By giving each well region its own voltage control, the system achieves local quality differentiation that enables precise erase operations without affecting other areas, improving erase operation efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient erase operations in units of sub-blocks, enhancing the productivity of semiconductor memory devices by maintaining a higher number of replaceable blocks and preventing unintentional data changes in unselected memory areas.
Implementation Method 1
The nonvolatile memory device is configured to perform an erase operation in units of the sub-blocks by independently applying an erase voltage to a selected one of the well regions during the erase operation
Data Source
AI summary
According to example embodiments, a nonvolatile memory device includes a lower filling insulating layer covering a peripheral logic structure on a substrate, a horizontal semiconductor layer on the lower filling insulating layer, and a three-dimensional memory cell array including a plurality of memory blocks on the horizontal semiconductor layer. The horizontal semiconductor layer includes a plurality of doped regions spaced apart from each other in a first direction and a plurality of well regions between the doped regions. Each of the memory blocks includes sub-blocks on corresponding ones of the well regions. The non-volatile memory device is configured to perform an erase operation in units of the sub-blocks. The non-volatile memory device is configured to independently apply an erase voltage to a selected one of the well regions during the erase operation.