Memory Subblock Segmentation for Power and Reliability

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Solution Overview

Problem

Conventional semiconductor memory devices face challenges in increasing integration density while maintaining reliability and reducing power consumption, as larger memory blocks exhibit reliability differences and high power consumption.

Innovation Solution

The memory device is divided into subblocks, where one subblock serves as a data buffer region, allowing independent operations such as write, read, and erase, and another subblock performs erase operations independently, optimizing power usage and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory block size is increased to improve integration density, then storage capacity is improved, but power consumption increases and reliability deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSUse of energy by stationary object

Solution Approach 1:

The memory block is divided into multiple subblocks (first subblock, second subblock, third subblock) that can be independently operated. This segmentation allows selective erasing of only the second subblock when needed, rather than erasing the entire memory block, thereby reducing power consumption while maintaining the ability to store large amounts of data across all subblocks.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If memory block size is increased to improve integration density, then storage capacity is improved, but reliability deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidmemory block reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The memory block is divided into multiple subblocks (first subblock, second subblock, third subblock) that can be independently operated. This segmentation allows selective erasing of only the second subblock when needed, rather than erasing the entire memory block, thereby reducing power consumption while maintaining the ability to store large amounts of data across all subblocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different subblocks are assigned different functions: the first and third subblocks store user data, while the second subblock serves as a data buffer region for metadata and temporary data. This local differentiation allows targeted operations on specific subblocks, improving reliability by isolating operations to only the necessary regions rather than affecting the entire memory block.

Inventive Principle:
Principle #3Local quality

3Reliability

If data buffer region is added to improve reliability, then memory lifespan is improved, but device complexity increases

Engineering Contradiction:
Improvememory device reliabilityVSAvoidmemory block structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The second subblock serves multiple functions: it acts as a data buffer region for storing metadata, serves as a temporary storage area during write operations, and can be independently erased without affecting user data in other subblocks. This multi-functionality reduces the need for separate dedicated buffer structures, thereby limiting the increase in device complexity while still improving reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240311054A1Memory device, operating method of memory device and memory system
Publication Date: 2024.09.19 SAMSUNG ELECTRONICS CO LTD
  • US20240311054A1 patent drawing
  • US20240311054A1 patent drawing
  • US20240311054A1 patent drawing

AI summary

Provided is a memory device including a plurality of memory blocks including of at least one subblock, wherein the memory block includes a first subblock configured to store first data including of at least one bit, and a second subblock configured to perform an erase operation independently of the first subblock and store second data including of at least one bit. The memory device is configured to perform a read operation on the second data in response to a write operation being performed on the second data in the second subblock. The memory device is configured to perform a write operation on the first data in the first subblock in response to a read operation being performed on the second data in the second subblock.