Memory Sub-Block Status Sensing During NAND Programming

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Solution Overview

Problem

Existing memory devices struggle to efficiently determine the programmed or erased condition of unselected sub-blocks within a memory block, leading to inefficiencies and potential errors during programming operations.

Innovation Solution

A method and apparatus for memory devices that involve segmenting word lines into sub-blocks and applying a reference voltage to all word lines of an unselected sub-block, performing a sensing operation to detect programmed or erased memory cells by measuring discharge current, and comparing it to a predetermined threshold.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a sensing operation is performed on only a single NAND string to detect unselected sub-block status, then device complexity is reduced, but measurement precision deteriorates

Engineering Contradiction:
Improvesensing operation complexityVSAvoidunselected sub-block status detection accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The memory block is divided into multiple sub-blocks (first sub-block and second sub-block), allowing the sensing operation to be performed on a single representative NAND string from the unselected sub-block. This segmentation enables status detection with reduced complexity while maintaining precision through strategic sampling of the sub-block structure.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If reference voltage is applied to all word lines of the unselected sub-block simultaneously, then measurement precision is improved, but use of energy increases

Engineering Contradiction:
Improveunselected sub-block status detection accuracyVSAvoidenergy consumption during sensing operation
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

Instead of applying reference voltage to all word lines of the unselected sub-block, the sensing operation is performed on a single representative NAND string. This partial action approach achieves sufficient measurement precision for status detection while significantly reducing the energy consumption compared to comprehensive sensing of all word lines.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If programming operation proceeds without verifying unselected sub-block status, then productivity is improved, but reliability deteriorates

Engineering Contradiction:
Improveprogramming operation speedVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A sensing operation is performed on a single NAND string from the unselected sub-block before proceeding with the programming operation on the selected sub-block. This preliminary action verifies the status of unselected sub-blocks, ensuring data integrity and preventing programming errors while maintaining high productivity through rapid single-string sensing.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for accurate and efficient detection of unselected sub-block conditions, reducing errors and improving programming efficiency by ensuring all word lines are evaluated simultaneously, thereby enhancing data integrity and operational reliability.

Implementation Method 1

performing a sensing operation on the word lines of the second sub-block... determining a discharge current through the at least one NAND string

Methodology Applied
Scientific EffectElectrical Conductivity: Conduction (electrical)

Data Source

PatentUS20260080949A1Technique to detect an unselected sub-block status in a memory device
Publication Date: 2026.03.19 SANDISK TECHNOLOGIES LLC
  • US20260080949A1 patent drawing
  • US20260080949A1 patent drawing
  • US20260080949A1 patent drawing

AI summary

The memory device that includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The plurality of word lines are segmented into a first sub-block and a second sub-block. The memory device also include circuitry that is configured to receive a programming command for the first sub-block and apply a reference voltage to a plurality of word lines of the second sub-block. The circuitry is further configured to perform a sensing operation on the word lines of the second sub-block. Based on results of the sensing operation, the circuitry is configured to establish whether the second sub-block contains programmed memory cells or does not contain programmed memory cells.