Memory Sub-Block Programming With Reduced Verification Loops
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing multi-pass programming method for flash memory requires excessive verification operations, leading to prolonged programming times due to unnecessary verify operations being performed during each programming step.
Innovation Solution
A memory device and method that reduces programming time by determining verify loop counts during non-last pass programming in memory sub-blocks and skipping the last verify operation for subsequent sub-blocks using the same program and verify conditions, thereby optimizing the programming process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-pass programming with verification operations is performed on all memory sub-blocks, then programming reliability is improved, but programming time is significantly increased
Solution Approach 1:
The patent applies local quality by differentiating the verification strategy between different memory sub-blocks. The first memory sub-block undergoes full multi-pass programming with verification operations to establish baseline reliability, while subsequent memory sub-blocks use a reduced verification strategy where the last verification operation is skipped, thereby reducing time loss while maintaining acceptable reliability levels.
Solution Approach 2:
The patent implements partial action by performing verification operations only to the extent necessary for the first memory sub-block, then reducing the verification action for subsequent sub-blocks. Specifically, the last verification operation is omitted for memory sub-blocks after the first one, assuming that the programming process has already been validated through the first sub-block's comprehensive verification.
2Productivity
If the last verification operation is skipped for subsequent memory sub-blocks, then programming speed is improved, but verification completeness may be compromised
Solution Approach 1:
The patent applies preliminary action by using the first memory sub-block as a pilot study to determine the necessary verification loop counts. The verification strategy established during the first sub-block's programming is then applied to subsequent sub-blocks, assuming that the preliminary verification has captured the essential reliability characteristics without requiring repeated verification on all sub-blocks.
Solution Approach 2:
The patent uses copying by replicating the programming process and verification loop counts from the first memory sub-block to subsequent memory sub-blocks. Instead of performing independent verification on each sub-block, the same verification parameters and loop counts determined during the first sub-block's programming are copied and applied to all other sub-blocks, thereby maintaining verification consistency while reducing overall time.
Data Source
AI summary
A memory device includes a memory array including memory blocks, and a control circuit coupled to the memory array. One of the memory blocks includes a first memory sub-block and a second memory sub-block. Each of the first memory sub-block and the second memory sub-block includes memory cells. The control circuit is configured to during a first program operation, perform a first number of verify operations on a first memory cell of the first memory sub-block, and during a second program operation after the first program operation, perform a second number of verify operations on a second memory cell of the second memory sub-block. A target program state of the first memory cell is the same as a target program state of the second memory cell, and the second number is smaller than the first number.