Memory Sub-Block Partial Program Voltage Control
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Solution Overview
Problem
Current memory devices face challenges in performing efficient partial program operations, particularly in scenarios where one sub-block is partially erased and another is programmed, leading to issues like program disturb due to lack of voltage transfer from a source line to the upper sub-block.
Innovation Solution
A memory device with control logic that applies a constant voltage to the word lines of a lower sub-block and a voltage lower than the program voltage to unselected word lines of an upper sub-block during a partial program operation, ensuring memory cells in the lower sub-block are turned on and boosting the upper sub-block, thereby preventing program disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a partial program operation is performed on an upper sub-block without voltage transfer from source line, then program operation can be performed on selected memory cells, but program disturb occurs due to lack of voltage transfer
Solution Approach 1:
The patent applies preliminary action by performing a precharge operation on the source line before the actual partial program operation. This precharge ensures that the source line has sufficient voltage to transfer to the upper sub-block during programming, preventing program disturb while enabling efficient partial program operations on erased memory blocks
Solution Approach 2:
The patent changes the voltage parameter of the source line by applying a precharge voltage that is higher than the normal operation voltage. This parameter change ensures adequate voltage transfer capability to the upper sub-block during partial program operations, resolving the contradiction between operation efficiency and reliability
2Reliability
If voltage is applied to all word lines during partial program operation, then memory cell functionality is maintained, but energy consumption increases
Solution Approach 1:
The patent applies local quality by differentiating voltage application across different sub-blocks. The lower sub-block (which is programmed) receives constant voltage on all word lines to maintain functionality, while the upper sub-block (which is erased) receives voltage only on selected word lines during partial program operations, reducing unnecessary energy consumption while maintaining reliability
Solution Approach 2:
The patent uses partial action by applying voltage to only the necessary word lines in the upper sub-block during partial program operations. Instead of applying voltage to all word lines in both sub-blocks, the system applies voltage selectively to maintain functionality where needed while minimizing energy consumption in areas where full voltage application is not required
Data Source
AI summary
A memory device includes a first sub-block including word lines, a second sub-block including word lines, and a peripheral circuit configured to apply voltages to the word lines of the first sub-block and the word lines of the second sub-block. The memory device also includes control logic configured to control the peripheral circuit to perform a partial program operation of storing data in the first sub-block, when a plurality of memory cells included in the first sub-block are erased and a plurality of memory cells included in the second sub-block are programmed. The control logic includes a program operation controller for controlling the peripheral circuit to apply a verify operation to a selected word line of the word lines of the first sub-block and then apply a voltage having a constant level to the word lines of the second sub-block in the partial program operation.