Memory Subchannel Switching for Defective Subsystem Recovery

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Solution Overview

Problem

Conventional memory devices with defective subsystems are rendered unusable, leading to discarded chips and reduced functionality due to manufacturing defects or operational failures, despite the availability of efficiency modes that could maintain partial functionality.

Innovation Solution

Implementing a multiplexer to dynamically switch between memory subchannels, enabling a single operational subsystem to control two subchannels, thereby maintaining full memory capacity with reduced bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a memory device operates in conventional mode with dedicated subsystems for each subchannel, then reliability is improved, but adaptability deteriorates when defects occur

Engineering Contradiction:
Improvesubsystem operational reliabilityVSAvoidsubchannel configuration adaptability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The first subsystem is designed to perform multiple functions: it can operate the first subchannel in conventional mode, or switch to operating the second subchannel in efficiency mode when a defect is detected. This multi-functionality allows the same hardware to adapt to different operational requirements and defect scenarios.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically switches between conventional mode and efficiency mode based on defect detection. The operational configuration is not fixed but can change in response to detected defects, allowing the memory device to adapt its subchannel assignment and maintain functionality.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If efficiency mode is implemented to allow single subsystem operation of two subchannels, then adaptability is improved, but reliability deteriorates due to increased operational load

Engineering Contradiction:
Improvesubchannel configuration adaptabilityVSAvoidsubsystem operational reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system performs defect detection beforehand to determine whether to operate in conventional mode or efficiency mode. By detecting defects in advance and switching modes proactively, the system prevents operational failures and ensures reliable operation under the chosen configuration.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If conventional operation is used with dedicated subsystems, then reliability is maintained, but loss of functionality increases when defects occur

Engineering Contradiction:
Improvesubsystem operational reliabilityVSAvoidmemory functionality loss
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

When a defect is detected in a dedicated subsystem, the system recovers functionality by reassigning the affected subchannel to the operational subsystem. Instead of discarding the entire memory device or losing the affected subchannel functionality, the system reallocates resources to maintain full operational capability.

Inventive Principle:
Principle #34Discarding and recovering

4Adaptability or versatility

If efficiency mode is activated to maintain full memory capacity, then functionality is preserved, but bandwidth is reduced

Engineering Contradiction:
Improvememory capacity utilizationVSAvoidmemory bandwidth
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The system implements efficiency mode as a partial action solution: instead of maintaining full dual-subsystem operation with maximum bandwidth, it accepts reduced bandwidth in exchange for maintaining full memory capacity utilization. This partial action approach prioritizes capacity availability over maximum throughput.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250356937A1Memory subsystem redundancy
Publication Date: 2025.11.20 INTEL CORP
  • US20250356937A1 patent drawing
  • US20250356937A1 patent drawing
  • US20250356937A1 patent drawing

AI summary

An apparatus includes a memory that includes a first memory subchannel and a second memory subchannel; a first memory subsystem; a multiplexer, configured to selectively connect the first memory subsystem to the first memory subchannel or the second memory subchannel; a second memory subsystem, connected to the second memory subchannel; and a processor, configured to control the multiplexer to connect the first memory subsystem to the first memory subchannel according to a first operational mode, or to selectively connect the first memory subsystem to the second memory subchannel according to a second operational mode, based on whether a defect is detected in the second memory subsystem.