Memory Sub-Channel Routing for PMEM Self-Refresh Power Savings
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Solution Overview
Problem
Existing memory systems face challenges in optimizing power consumption and latency due to the coexistence of persistent and non-persistent memory types, particularly in systems with dual memory hierarchies, where power management is inefficient and sub-optimal.
Innovation Solution
Implementing a memory controller that routes memory transactions across independent sub-channels within a DDR5 DIMM, allowing one sub-channel to enter a self-refresh mode while maintaining active persistent memory transactions on another, thereby optimizing power usage and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used for main memory to achieve high performance and low latency, then access speed is improved, but power consumption increases and memory capacity is limited
Solution Approach 1:
The patent merges persistent memory (PMEM) and non-persistent memory (DRAM) into a unified memory hierarchy, allowing the system to leverage the high speed of DRAM for frequently accessed data while using the high capacity and low power consumption of PMEM for less frequently accessed data, thus resolving the contradiction between speed and power consumption
Solution Approach 2:
The patent segments the memory system into distinct persistent and non-persistent memory domains with independent controllers and routing mechanisms, enabling selective activation of power-saving modes in PMEM while maintaining high-speed access to DRAM, thereby optimizing the balance between performance and power consumption
2Quantity of substance
If NAND memory is used to increase storage capacity, then memory capacity is improved, but access latency increases
Solution Approach 1:
The patent segments the memory hierarchy into multiple levels with different characteristics: PMEM provides high-capacity storage with low latency, while DRAM provides high-speed access for frequently accessed data, thereby reducing the overall access latency compared to using NAND alone while maintaining high capacity
Solution Approach 2:
The patent introduces a new dimension to the memory hierarchy by integrating PMEM between CPU and DRAM, creating a three-tier structure that adds capacity without sacrificing latency, as PMEM can be accessed with latency similar to DRAM while providing NAND-like capacity
3Loss of energy
If power management is optimized by entering self-refresh mode, then power consumption is reduced, but transaction routing complexity increases
Solution Approach 1:
The patent implements feedback mechanisms where memory controllers continuously monitor transaction patterns and power states, dynamically adjusting routing decisions to enter self-refresh mode when appropriate while maintaining performance, thus reducing power consumption without excessive complexity through intelligent control
Solution Approach 2:
The patent makes the memory system dynamic by allowing real-time adjustment of routing paths and power states based on workload conditions, enabling the system to adaptively balance between power savings and performance requirements through flexible, condition-based routing decisions
4Productivity
If dual memory hierarchies are implemented, then overall system performance is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory control functions into separate controllers for PMEM and DRAM, each managing its own domain independently, which simplifies the overall system architecture despite the dual hierarchy by dividing complexity into manageable, independent modules
Solution Approach 2:
The patent creates a universal memory subsystem that handles both PMEM and DRAM transactions through a unified addressing and routing infrastructure, allowing a single memory controller to manage diverse memory types with different characteristics, thereby reducing overall system complexity while maintaining high performance
Data Source
AI summary
An apparatus for processing data is provided comprising persistent memory circuitry, non-persistent memory circuitry and memory controller circuitry. The memory controller circuitry provides two or more memory sub-channels and each memory sub-channel is for routing of memory access transactions for at least one of the persistent memory circuitry and the non-persistent memory circuitry. The memory controller circuitry has channel selection circuitry to detect when there are no non-persistent memory transactions on one of the two or more memory sub-channels and responsive to the detection, is to route any persistent memory transactions to a different one of the two or more memory sub-channels. A memory controller apparatus, a persistent memory Dual In-line Memory Module, a method and computer program are also provided.