Memory Device Subcore Preprocessing for Lower Access Latency
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Solution Overview
Problem
Existing memory devices and storage devices face challenges in reducing latency due to the lack of efficient preprocessing tasks before accessing target locations in memory regions, leading to inefficient operation performance.
Innovation Solution
The implementation of a memory device with a main core controlling subcores to perform preprocessing tasks in response to preprocessing commands, and a controller that determines and transmits preprocessing commands to the memory device, allowing for parallel execution of tasks through semaphore management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If preprocessing tasks are performed before accessing target locations in memory regions, then operation performance is improved, but device complexity increases due to the need for main core and subcore architecture with semaphore management
Solution Approach 1:
The memory device is divided into a main core and multiple subcores, where the main core handles preprocessing tasks and subcores handle main tasks. This segmentation allows parallel execution of different task types, improving overall operation performance while distributing computational load across specialized units.
Solution Approach 2:
The main core performs preprocessing tasks (such as address translation, data validation, and preprocessing operations) before the actual memory access tasks are executed by subcores. This preliminary action prepares the data and addresses in advance, reducing the latency of main tasks and improving operation performance.
2Loss of time
If multiple subcores perform tasks in parallel, then latency is reduced, but control complexity increases due to semaphore management requirements
Solution Approach 1:
A semaphore management mechanism is introduced as an intermediary between the main core and subcores. The semaphore acts as a synchronization tool that coordinates task execution, allows subcores to be dynamically unlocked and locked based on task completion status, and manages parallel execution without requiring complex inter-subcore communication protocols.
Solution Approach 2:
The system dynamically manages subcore states through semaphores, allowing subcores to be unlocked for task execution and locked upon completion. This dynamic state management enables flexible parallel execution where subcores can be activated and deactivated based on task requirements, reducing latency while maintaining manageable control complexity through standardized semaphore operations.
Data Source
AI summary
A memory device may include a plurality of subcores and a main core configured to control a subcore of the plurality of subcores to perform a preprocessing task of a memory operation in response to a preprocessing command.