Non-Volatile Memory Sub-Counter Layout for Write-Endurance Limits
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Solution Overview
Problem
Non-volatile memory transaction counters face limitations due to the limited lifetime of storage cells in terms of write operations, requiring more memory cells than necessary to count transactions beyond a certain endurance, leading to inefficient use of memory resources.
Innovation Solution
Implementing a counter in non-volatile memory with multiple sub-counters, each counting with a different modulo, allowing incremental updates on a single sub-counter and using the Chinese remainder theorem for result reconstruction, thereby reducing the number of bits or bytes required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more non-volatile memory cells are used to extend counter capacity beyond write cycle limits, then the counter can handle more transactions, but the memory resource usage increases significantly
Solution Approach 1:
The patent divides a single counter into multiple sub-counters, each capable of independent increment operations. This segmentation allows the system to rotate through different sub-counters, performing write operations on only one sub-counter at a time, thereby extending the effective write cycle capacity without proportionally increasing total memory usage.
Solution Approach 2:
The patent changes the operational parameters by implementing different modulo values for each sub-counter. Each sub-counter operates with a specific modulo (e.g., 2, 3, 4, 5), allowing the system to track transactions beyond the write cycle limit of individual memory cells by mathematical reconstruction using the Chinese Remainder Theorem.
2Duration of action of stationary object
If multiple sub-counters are implemented with different modulos, then write cycle endurance is extended, but the device complexity increases
Solution Approach 1:
The counter is segmented into multiple sub-counters with different modulo values, allowing the system to distribute write operations across multiple smaller units. This segmentation extends write cycle endurance by ensuring that not all memory cells are written simultaneously, reducing wear on any single cell.
Solution Approach 2:
The patent introduces a reconstruction function based on the Chinese Remainder Theorem as an intermediary mechanism. This mathematical approach allows the system to reconstruct the total transaction count from the individual sub-counter values, managing the complexity of coordinating multiple sub-counters with different modulos.
3Device complexity
If a single counter is used to count all transactions, then the structure is simple, but the counter cannot handle transactions beyond the write cycle limit
Solution Approach 1:
The patent segments the counter into multiple sub-counters, each handling a portion of the transaction counting. This segmentation enables the system to count transactions beyond the write cycle limit of individual memory cells by rotating through different sub-counters and using mathematical reconstruction to determine the total count.
Data Source
AI summary
A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.