On-Die Memory Sub-Module Power Management for Leakage Reduction
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Solution Overview
Problem
Integrated circuit devices face challenges in achieving high operating frequencies during active use-cases while minimizing power consumption during inactive periods due to high power leakage in on-die buffers, which limits the reduction in power consumption.
Innovation Solution
A power management module dynamically controls the power state of on-die memory sub-modules by determining when content is redundant and powering down or placing it into a low-power state, ensuring only required sub-modules are fully powered up, thereby reducing overall power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high frequency fabrication processes are used to achieve high operating frequencies during high activity use-cases, then operating frequency is improved, but power leakage increases
Solution Approach 1:
The on-die buffer is divided into multiple independently controllable sub-modules. Each sub-module can be individually powered down or placed in low-power state based on whether its content is still needed, allowing selective power management that reduces overall power leakage while maintaining high frequency operation when needed.
Solution Approach 2:
The power state of buffer sub-modules is dynamically adjusted based on real-time needs. The system transitions sub-modules between fully powered-up, low-power, and powered-down states according to whether their content is currently required, enabling adaptive power management that balances performance and power consumption.
2Ease of operation
If on-die buffer remains powered-up during CPU inactive periods to allow data access by other on-die modules, then data accessibility is improved, but power consumption increases
Solution Approach 1:
The buffer is segmented into multiple sub-modules with independent power control. This allows only the necessary portions to remain powered-up for data access while other portions are powered-down, eliminating the need to keep the entire buffer powered-up and reducing overall power consumption during CPU inactive periods.
Solution Approach 2:
Different power states are applied to different regions of the buffer based on local needs. Sub-modules containing actively needed data maintain full power for immediate access, while sub-modules with redundant or less critical data are placed in low-power or powered-down states, creating localized power management that balances accessibility and power consumption.
3Reliability
If more on-die buffer sub-modules are kept fully powered-up to ensure data availability, then data accessibility is improved, but power leakage increases
Solution Approach 1:
By segmenting the buffer into independently controllable sub-modules, the system can precisely control which portions remain powered-up based on actual data availability needs. This prevents unnecessary power consumption in sub-modules whose data is already available elsewhere or no longer needed, while ensuring critical sub-modules remain powered-up for data availability.
Solution Approach 2:
The power management module continuously monitors which buffer sub-modules contain data that is currently needed and adjusts power states accordingly. This feedback mechanism ensures that only the minimum necessary sub-modules remain fully powered-up to maintain data availability, automatically reducing power leakage when data becomes redundant or is moved to other locations.
Data Source
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AI summary
An integrated circuit device (100) comprising at least one memory module (120) comprising a plurality of memory sub-modules (320, 420, 520, 525), and at least one power management module (170) arranged to provide power management for the at least one memory module (120). The at least one power management module (170) is arranged to determine when content of at least one memory sub-module (320, 420, 520, 525) is redundant, and place the at least one memory sub-module (320, 420, 520, 525) into a powered-down state upon determining that content of the at least one memory sub-module (320, 420, 520, 525) is redundant.