Memory Substitution Circuitry for Firmware Update Flexibility

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Solution Overview

Problem

Existing memory systems face challenges in efficiently modifying and updating executable code, as hard-coded firmware changes are expensive and time-consuming, limiting flexibility and the ability to add new features or debug existing algorithms.

Innovation Solution

A memory system with a control unit and substitution circuitry that allows for the execution of both hard-coded and dynamically updated executable instructions, enabling seamless switching between different instruction sequences stored in ROM and SRAM, facilitating modifications and additions to the algorithm without recompilation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If firmware is hard-coded into memory device, then reliability is improved, but adaptability deteriorates

Engineering Contradiction:
Improvefirmware reliabilityVSAvoidcode update capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent segments the firmware storage into two distinct parts: a first portion stored in non-volatile memory (ROM) for reliable execution, and a second portion stored in volatile memory (RAM) for flexible updates. This segmentation allows the system to maintain reliability by preserving the core hard-coded firmware while gaining adaptability through the ability to update the volatile memory portion without affecting the stable ROM-based operations.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If firmware is hard-coded into memory device, then manufacturing precision is improved, but ease of repair deteriorates

Engineering Contradiction:
Improvefirmware integrationVSAvoidfirmware update difficulty
Core Design Contradiction:
Manufacturing precisionVSEase of repair

Solution Approach 1:

The patent introduces dynamic characteristics to the traditionally static hard-coded firmware by implementing a dual-memory architecture where the volatile memory portion can be updated during operation. This allows the firmware to transition from a fixed state to a flexible state, enabling repairs and updates without requiring costly re-manufacturing processes while maintaining the precision-integrated ROM portion.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If code updates are implemented, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improvecode modification capabilityVSAvoidmemory system structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a intermediary control mechanism that manages the interaction between ROM and RAM portions of the firmware. This intermediary layer handles the complexity of coordinating updates, managing memory access, and ensuring smooth transitions between different code versions, thereby reducing the perceived complexity for users while maintaining high adaptability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11163572B2Memory systems and memory control methods
Publication Date: 2021.11.02 MICRON TECHNOLOGY INC
  • US11163572B2 patent drawing
  • US11163572B2 patent drawing
  • US11163572B2 patent drawing

AI summary

Memory systems and memory control methods are described. According to one aspect, a memory system includes a plurality of memory cells individually configured to store data, program memory configured to store a plurality of first executable instructions which are ordered according to a first instruction sequence and a plurality of second executable instructions which are ordered according to a second instruction sequence, substitution circuitry configured to replace one of the first executable instructions with a substitute executable instruction, and a control unit configured to execute the first and second executable instructions to control reading and writing of the data with respect to the memory, wherein the control unit is configured to execute the first executable instructions according to the first instruction sequence, to execute the substitute executable instruction after the execution of the first executable instructions, and to execute the second executable instructions according to the second instruction sequence as a result of execution of the substitute executable instruction.