Memory Module Substrate Via Layout With Capacitive Crosstalk Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor memory module products require higher signal density, crosstalk interference between signal lines occurs, degrading product characteristics, and maximizing signal line separation is limited by spatial constraints.
Innovation Solution
A substrate for semiconductor modules is designed with insulating layers and signal lines featuring vias arranged in a polygon shape, along with capacitor elements providing capacitive coupling between signal lines to compensate for signal speed differences and prevent crosstalk, allowing for flexible configuration of capacitive patterns and arrangements to address crosstalk effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If signal line separation is maximized to prevent crosstalk, then signal interference is reduced, but spatial constraints are exceeded
Solution Approach 1:
The patent introduces capacitor elements as intermediary components between adjacent signal lines. These capacitors act as mediators that equalize potential differences and signal speeds between neighboring lines, thereby reducing crosstalk interference without requiring increased spatial separation. The capacitor elements are positioned at specific locations where signal lines are most prone to interference, providing localized compensation that maintains compact module dimensions.
Solution Approach 2:
The patent changes the electrical parameters of signal lines by introducing capacitive coupling elements. The capacitors modify the signal transmission characteristics by adding controlled capacitance between adjacent lines, which alters signal speed and impedance matching. This parameter modification allows signal lines to maintain closer spacing while still achieving acceptable signal integrity and reduced crosstalk through electrical parameter optimization rather than spatial separation.
2Productivity
If signal density is increased to meet higher specifications, then product performance is improved, but crosstalk interference increases
Solution Approach 1:
The patent applies parameter changes by introducing capacitor elements that modify the electrical characteristics of high-density signal lines. The capacitors compensate for signal speed variations and impedance mismatches that become more pronounced at higher signal densities. By adjusting the capacitance values and positions, the system maintains signal integrity even when signal lines are closely spaced to achieve high density.
Solution Approach 2:
Capacitor elements serve as intermediary components between closely spaced signal lines in high-density configurations. These intermediaries provide controlled coupling that prevents harmful crosstalk while allowing beneficial signal synchronization. The capacitors are strategically placed at locations where high-density routing creates maximum interference risk, enabling the system to achieve high signal density without proportionally increasing crosstalk.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capacitive coupling between signal lines improves signal characteristics by compensating for speed differences and preventing crosstalk, even in structures where interference is likely to occur, enhancing the performance of semiconductor memory modules.
Implementation Method 1
a capacitor element configured to provide capacitive coupling between the N signal lines
Data Source
AI summary
A substrate for semiconductor module includes a plurality of insulating layers sequentially stacked on one another, N signal lines transmitting N signals respectively, the N signal lines having N vias that at least partially penetrate through the plurality of insulating layers and are arranged in an N-sided polygon shape in a plan view, and a capacitor element configured to provide capacitive coupling between the N signal lines, the capacitor element having a first coupling element that provides capacitive coupling between first and second vias adjacent to each other among the N vias and a second coupling element that provides capacitive coupling between third and fourth vias that are not adjacent to each other among the N vias.