Bonded Memory Substrate Layout With SOI Transistors for Smaller Chips
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Solution Overview
Problem
The existing memory devices with bonded CMOS and memory substrates face challenges in maintaining equivalent chip sizes and reducing manufacturing costs due to increased transistor counts and chip area expansion, which affects storage capacity and efficiency.
Innovation Solution
The memory device integrates part of the CMOS circuit on the memory substrate, utilizing a silicon-on-insulator (SOI) structure for transistors, allowing for reduced chip size and manufacturing costs by distributing high-voltage transistors on the same plane as the memory cell array, thereby minimizing leakage current and chip expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If part of the CMOS circuit is integrated on the memory substrate, then chip size is reduced and manufacturing costs are reduced, but transistor leakage current may increase
Solution Approach 1:
The patent merges the CMOS circuit and memory cell array onto the same memory substrate, integrating high-voltage transistors for word line switching directly with the memory cells. This consolidation eliminates the need for separate CMOS substrate bonding, reducing overall chip size while maintaining functional separation through careful circuit design and substrate integration techniques.
Solution Approach 2:
The patent changes the substrate parameter from separate bonded substrates to a single integrated memory substrate, and modifies transistor structure parameters to optimize leakage current characteristics. By adjusting device-level parameters such as transistor threshold voltages and substrate biasing schemes, the patent achieves low leakage current despite high-voltage transistor integration.
2Area of stationary object
If high-voltage transistors are distributed on the same plane as the memory cell array, then chip expansion is minimized, but manufacturing complexity increases
Solution Approach 1:
The patent segments the memory substrate into distinct functional regions: a memory cell array region and a high-voltage transistor region. This spatial segmentation allows different manufacturing processes to be applied to different areas, with the word line switch units positioned adjacent to the memory cell array for optimized connectivity while maintaining manufacturing feasibility through zone-based process control.
Solution Approach 2:
The patent utilizes vertical stacking in the third dimension to accommodate both high-voltage transistors and memory cells on the same substrate plane. By employing multi-layer interconnect structures and vertical signal routing, the patent achieves three-dimensional integration that minimizes planar chip area expansion while managing manufacturing complexity through layered architecture.
3Ease of manufacture
If the number of wiring layers is minimized, then manufacturing costs are reduced, but circuit connectivity may be compromised
Solution Approach 1:
The patent employs dynamic signal routing and multiplexing schemes that allow a reduced number of wiring layers to achieve full circuit connectivity. By implementing time-division multiplexing for control signals and dynamic voltage switching for data lines, the patent maintains reliable connectivity with fewer physical wiring layers, reducing manufacturing complexity while preserving functional completeness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces chip size and manufacturing costs by maintaining equivalent chip sizes for CMOS and memory substrates, enhancing storage capacity and reducing leakage current through the SOI structure, while minimizing the number of wiring layers and film thickness.
Implementation Method 1
utilizing a silicon-on-insulator (SOI) structure for transistors, allowing for reduced chip size and manufacturing costs by distributing high-voltage transistors on the same plane as the memory cell array, thereby minimizing leakage current
Data Source
AI summary
According to one embodiment, a memory device includes a first substrate and a second substrate. The first substrate is provided with a first circuit layer on a front surface. The first circuit layer includes a CMOS circuit. The second substrate has a front surface that faces the first substrate. The second substrate is provided with a second circuit layer on the front surface contacting the first circuit layer. The second substrate includes a memory circuit and transistors of a silicon-on-insulator (SOI) structure.