Memory Substrate Wiring Layout for Warpage and Noise Control
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Solution Overview
Problem
In semiconductor memory systems, the warpage of thinned, rectangle-shaped substrates is a challenge due to thermal expansion coefficient differences between layers, leading to convex shape deformations and increased risk of substrate warpage, especially during miniaturization and manufacturing processes.
Innovation Solution
The semiconductor memory system employs a multilayer substrate with adjusted wiring densities, particularly in the eighth layer, to equalize thermal expansion coefficients across layers, and uses an adhesive portion to counteract warpage forces, while also incorporating a meshed wiring pattern and slits in the seventh layer to reduce noise interference and simplify wiring design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the substrate is thinned for miniaturization, then the size is reduced, but the warpage of substrate increases
Solution Approach 1:
The patent adjusts the wiring density parameter in the eighth layer of the substrate to equalize thermal expansion coefficients across layers. By changing the physical parameter of wiring density, the substrate maintains dimensional stability despite being thinned for miniaturization, thus resolving the contradiction between reduced size and suppressed warpage.
2Adaptability or versatility
If different materials are used in substrate layers, then functionality is improved, but thermal expansion coefficient differences cause warpage
Solution Approach 1:
The patent applies local quality by creating a specific wiring density distribution in the eighth layer rather than using uniform material properties throughout. This localized adjustment of wiring density compensates for thermal expansion differences between different material layers, allowing functional diversity while maintaining overall substrate stability.
3Productivity
If wiring density is increased for miniaturization, then integration is improved, but noise interference increases
Solution Approach 1:
The patent implements different wiring density characteristics in different layers: the eighth layer has adjusted wiring density for thermal expansion control, while the seventh layer uses a meshed pattern with slits for noise reduction. This localized differentiation allows high integration density while managing noise interference through spatially varying wiring structures.
Solution Approach 2:
The wiring structure is segmented into different patterns across layers - particularly the meshed pattern with slits in the seventh layer - to separate signal transmission functions from thermal management functions. This segmentation allows each layer to optimize for its specific purpose while working together to achieve both high integration and low noise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses substrate warpage, maintains equal wiring densities across layers, and reduces noise interference, thereby enhancing the stability and reliability of the semiconductor memory system, especially in miniaturized designs.
Implementation Method 1
uses an adhesive portion to counteract warpage forces
Implementation Method 2
adjusted wiring densities, particularly in the eighth layer, to equalize thermal expansion coefficients across layers
Data Source
AI summary
According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.