Non-Volatile Memory Device Substring Segmentation for Reliability
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Solution Overview
Problem
Conventional NAND type non-volatile memory devices rely on channel boosting technology to inhibit programming on unselected NAND strings, which can damage outermost memory transistors and reduce operation reliability due to hot carrier effects and short channel issues.
Innovation Solution
A non-volatile memory device architecture that operates without channel boosting, utilizing main strings with first and second substrings, charge supply lines, and selection transistors to selectively control programming and reading of memory cell transistors, forming flash memory with a perpendicular structure and using fringe fields to form source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel boosting technology is used to inhibit programming on unselected NAND strings, then programming inhibition is achieved, but memory transistor damage occurs and operation reliability decreases
Solution Approach 1:
The NAND string is divided into multiple substrings (first substring and second substring), each with its own selection transistor. This segmentation allows selective programming of specific substrings without requiring channel boosting on the entire string, thereby preventing hot carrier damage while maintaining programming inhibition capability.
Solution Approach 2:
Different voltage conditions are applied to different substrings within the same NAND string. The selected substring receives programming voltages while unselected substrings are inhibited through their selection transistors, allowing localized programming without global channel boosting and its associated damage.
2Reliability
If high boosting voltage is applied to channels of unselected NAND strings, then programming inhibition is achieved, but outermost memory transistors are damaged
Solution Approach 1:
The harmful channel boosting voltage application is extracted and replaced with a selection transistor-based inhibition mechanism. Instead of applying high voltages to unselected strings, the patent uses selection transistors to locally control which substrings receive programming voltages, eliminating the need for damaging boosting voltages.
Solution Approach 2:
Selection transistors act as intermediaries between the programming voltage sources and the memory transistors. These transistors control the flow of programming voltages to specific substrings, preventing direct exposure of unselected memory transistors to high voltages and thus avoiding damage.
3Reliability
If channel boosting is used to inhibit programming on unselected strings, then data inhibition is achieved, but short channel effects occur during read operations
Solution Approach 1:
Dividing the NAND string into multiple substrings with individual selection transistors allows precise control of programming and read operations. This segmentation eliminates the need for channel boosting to inhibit unselected strings, thereby preventing short channel effects while maintaining data storage reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable programming and reading operations without applying high boosting voltages, thereby preventing damage to memory transistors and improving the overall operation reliability of the non-volatile memory device.
Implementation Method 1
Source and drain regions may be formed on a semiconductor substrate between the memory cell transistors by fringe fields. The fringe fields may be formed by applying voltages to gates of the memory cell transistors.
Data Source
AI summary
The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor. A method of programming a target cell of the memory device includes activating selection transistors connected to a main string and substring of the target cell.