Memory Subsystem Adaptive Programming Mode Selection

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Solution Overview

Problem

Existing memory systems face challenges in optimizing performance due to errors in reading data from memory cells, particularly as the threshold voltage of memory cells drifts over time, leading to increased bit error rates and longer read operations when storing multiple bits per cell.

Innovation Solution

A memory sub-system that adaptively selects a programming mode for memory cells based on usage parameters and error recovery options to optimize storage capacity and reduce read retry, using a predictive model to determine the appropriate mode for storing data, such as Single Level Cell (SLC), Multi-Level Cell (MLC), Triple Level Cell (TLC), or Quad-Level Cell (QLC) modes, and incorporating redundant information for error detection and recovery.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple bits per cell are stored to increase storage capacity, then storage density is improved, but bit error rate increases due to threshold voltage drift

Engineering Contradiction:
Improvestorage capacityVSAvoidbit error rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies dynamics by making the programming mode adaptive rather than fixed. The system dynamically selects between SLC, MLC, TLC, and QLC modes based on real-time usage parameters and error recovery options, allowing the storage system to optimize between capacity and reliability as conditions change

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of programming mode (SLC/MLC/TLC/QLC) based on usage parameters and error recovery needs. By adjusting this parameter, the system can shift between high-reliability low-capacity modes and high-capacity lower-reliability modes to resolve the contradiction

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If multiple bits per cell are stored to increase storage capacity, then storage density is improved, but read operation time increases due to read retry

Engineering Contradiction:
Improvestorage capacityVSAvoidread operation time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent performs preliminary action by predicting the optimal programming mode before data is written. The predictive model analyzes usage parameters in advance and selects the appropriate mode (SLC/MLC/TLC/QLC), preventing future read retries by making the right choice upfront

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using usage parameters and error recovery options to inform the programming mode selection. The system continuously monitors performance and adjusts the programming mode based on this feedback, reducing read operation time through adaptive optimization

Inventive Principle:
Principle #23Feedback

3Productivity

If adaptive programming mode selection is implemented to optimize performance, then read operation efficiency is improved, but device complexity increases

Engineering Contradiction:
Improveread operation efficiencyVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies self-service by implementing a predictive model that automatically selects the optimal programming mode without requiring complex external control. The system serves itself by using usage parameters to make intelligent decisions about programming mode selection

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent achieves universality by creating a programming manager that handles multiple functions: predicting optimal modes, selecting programming modes, managing error recovery, and adapting to different usage scenarios. This single multi-functional component resolves the contradiction by consolidating complexity into a manageable universal controller

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240404606A1Identify the programming mode of memory cells during reading of the memory cells
Publication Date: 2024.12.05 MICRON TECHNOLOGY INC
  • US20240404606A1 patent drawing
  • US20240404606A1 patent drawing
  • US20240404606A1 patent drawing

AI summary

Systems, methods and apparatus to determine a programming mode of a set of memory cells that store an indicator of the programming mode. In response to a command to read the memory cells in a memory device, a first read voltage is applied to the memory cells to identify a first subset of the memory cells that become conductive under the first read voltage. The determination of the first subset is configured as an operation common to different programming modes. Based on whether the first subset of the memory cell includes one or more predefined memory cells, the memory device determines a programming mode of memory cells. Once the programming mode is identified from the common operation, the memory device can further execute the command to determine a data item stored, via the programming mode, in the memory cells.