Multi-Class Memory Subsystem with Buffer Chip for Dynamic Thread Allocation
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Solution Overview
Problem
Current memory systems face inefficiencies in utilizing multiple memory technologies, leading to slower system performance due to the need to access slower memory classes, which can significantly impact memory bandwidth and speed.
Innovation Solution
A memory subsystem that combines a first memory of a first memory class and a second memory of a second memory class, communicatively coupled to facilitate efficient data fetching and management through a single memory bus, allowing for dynamic allocation and reclassification of memory functions between different classes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a hierarchical memory system with DRAM and NAND flash is used, then storage capacity is improved, but access time increases
Solution Approach 1:
The memory system is segmented into multiple memory classes (first memory class and second memory class) that can be independently accessed. The buffer chip divides the memory address space into different segments, allowing simultaneous access to different memory classes for different threads, thereby reducing the time penalty of having large storage capacity.
Solution Approach 2:
The patent introduces a new dimension of parallelism by enabling multi-thread operations where different threads can access different memory classes simultaneously. This transforms the single-thread sequential access model into a multi-thread parallel access model, effectively reducing access time while maintaining large storage capacity.
2Quantity of substance
If a hierarchical memory system with DRAM and NAND flash is used, then storage capacity is improved, but power consumption increases
Solution Approach 1:
The memory system dynamically allocates and reclassifies memory functions based on operational needs. The buffer chip can dynamically reclassify memory addresses between different memory classes, allowing the system to adapt power consumption to actual workload requirements, reducing unnecessary power usage while maintaining required storage capacity.
Solution Approach 2:
The system changes the operational parameters of different memory classes based on thread activity. When certain memory regions are not actively accessed, the system can power down or reduce activity in those memory classes, thereby reducing overall power consumption while maintaining the storage capacity when needed.
3Productivity
If multi-thread operations are implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
The buffer chip acts as an intermediary between the processor and the multiple memory classes. It handles the complexity of memory management, address translation, and thread coordination internally, presenting a simplified interface to the processor while enabling complex multi-thread operations across different memory classes.
Solution Approach 2:
The buffer chip is designed with universal functionality to handle multiple memory classes, multiple threads, and various memory operations simultaneously. This multi-functional design consolidates what would otherwise require separate dedicated hardware for each function, reducing overall device complexity while enabling high productivity through multi-thread operations.
Data Source
AI summary
An apparatus, computer program product, and associated method/processing unit are provided for utilizing a memory subsystem including a first memory of a first memory class, and a second memory of a second memory class communicatively coupled to the first memory. In operation, data is fetched using a time between a plurality of threads.