Memory Subsystem Coherency via Intermediate Write Buffer Mapping
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Solution Overview
Problem
Conventional memory sub-systems face coherency issues during logical to physical page translation, leading to read operation failures due to incomplete write operations, which are addressed by introducing additional modules and processing complexity.
Innovation Solution
A data structure with intermediate entries and pointers to write buffers is implemented to manage in-process write operations, allowing for successful servicing of read requests by copying data from write buffers to read buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the L2P table is updated with the physical address of the target memory device during an interval after the L2P table has been updated but before the write operation is complete, then the translation speed is improved, but read operation failures occur due to coherency issues
Solution Approach 1:
The patent applies preliminary action by updating the L2P table with the physical address before the write operation is complete, allowing subsequent read operations to be directed to the correct physical location in advance. This enables the system to prepare the translation mapping ahead of time, improving translation speed while the coherency check ensures read reliability by verifying write completion status before servicing read requests.
2Reliability
If conventional memory sub-systems implement a separate module to manage hash table and coherency checking, then coherency issues are resolved, but device complexity and performance are negatively impacted
Solution Approach 1:
The patent merges the coherency checking functionality into the existing map translation component, eliminating the need for a separate coherency checking module. The map translation component now handles both address translation and coherency verification by checking whether a physical address corresponds to a valid memory location, thereby resolving coherency issues while reducing device complexity and improving performance.
3Reliability
If conventional memory sub-systems use a separate module for coherency checking, then read operation coherency is ensured, but productivity is reduced due to extra cycling
Solution Approach 1:
The patent combines coherency checking with the address translation process in the map translation component. By integrating these functions, the system performs coherency verification as part of the normal translation workflow without requiring separate processing cycles, thereby ensuring read operation coherency while maintaining high productivity and avoiding the performance penalty of extra cycling.
Data Source
AI summary
A write request to program data to a memory device of a memory sub-system is received. An intermediate entry of a data structure is generated, the intermediate entry including a pointer identifying a write buffer associated with an intermediate write operation corresponding to the write request. A read request to read the data from the memory device is received and a look-up operation of the data structure is performed to identify the intermediate entry. Using the pointer to locate the write buffer associated with the intermediate write operation. The write buffer is copied to a read buffer associated with the read request and the read request is executed using the read buffer.