Memory Subsystem Command Fetching via Zone-Plane Mapping

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Solution Overview

Problem

Existing memory sub-systems face inefficiencies in command fetching due to the inability to achieve maximum parallelism across multiple dice, particularly when using smaller zone sizes that map to block sets within a single die.

Innovation Solution

The implementation of a zone-to-plane set mapping table in the memory sub-system controller allows for efficient command fetching by identifying fixed mappings of each zone to a corresponding plane set, enabling the storage of memory access operations in queues specific to each plane set and optimizing command execution for maximum parallelism.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If smaller zone sizes are used that map to block sets within a single die, then memory access precision is improved, but parallelism across multiple dice is reduced

Engineering Contradiction:
Improvememory access precisionVSAvoidparallelism
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The command queue is segmented into multiple sub-queues, with each sub-queue associated with a specific die. This allows commands to be distributed across multiple dice for parallel execution, resolving the contradiction between precise zone mapping and parallelism by organizing command processing along the die dimension rather than the zone dimension.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension for command organization by mapping commands to dice instead of organizing them solely by zone. This dimensional shift allows the system to maintain precise zone-to-block-set mapping while achieving parallelism through die-level distribution of command queues.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If commands are fetched without die-aware queue organization, then device complexity is reduced, but command fetching efficiency deteriorates

Engineering Contradiction:
Improvequeue organization complexityVSAvoidcommand fetching efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The command queue is divided into multiple sub-queues, each dedicated to a specific die. This segmentation enables efficient command fetching by allowing the controller to fetch commands from multiple sub-queues in parallel, improving command fetching efficiency while maintaining manageable complexity through the structured organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Commands are pre-sorted and distributed into die-specific sub-queues before execution. This preliminary organization allows the controller to efficiently fetch commands from appropriate sub-queues based on the target die, improving command fetching efficiency without requiring complex real-time decision-making during execution.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250053344A1Efficient command fetching in a memory sub-system
Publication Date: 2025.02.13 MICRON TECHNOLOGY INC
  • US20250053344A1 patent drawing
  • US20250053344A1 patent drawing
  • US20250053344A1 patent drawing

AI summary

A system includes a memory device configured with a zoned namespace having a plurality of zones, and a processing device, operatively coupled with the memory device, to perform operations comprising storing, in a first queue of the memory device, a first identifier of a first memory access operation to be performed at a first zone of the memory device, identifying one of a plurality of plane sets of the memory device that is associated with the first zone of the memory device, identifying a second queue of the memory device, wherein the second queue corresponds to the identified plane set, responsive to determining that a number of identifiers of memory access operations stored in the second queue satisfies a threshold criterion, retrieving, from the second queue, a second identifier of a second memory access operation to be performed at a second zone of the memory device, storing the second identifier of the second memory access operation in a third queue of the memory device, and performing the second memory access operation at the second zone associated with a second plane set of the memory device.