Memory Sub-System Deferred Parity Calculation
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Solution Overview
Problem
Conventional memory sub-systems face performance penalties and increased memory resource usage due to the need for parallel error-correction parity calculations, particularly in RAIN techniques, which can lead to significant overhead and degradation in sequential read performance.
Innovation Solution
The system defers error-correction parity calculations until the memory sub-system is in an idle state, allowing for background processing and reducing the need for temporary memory usage, thereby decoupling parity data storage from user data and minimizing performance penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parallel error-correction parity calculations are performed in conventional memory sub-systems, then data protection reliability is improved, but memory resource usage increases and performance degrades
Solution Approach 1:
The patent performs error-correction parity calculations during idle periods before they are actually needed for data recovery. By pre-calculating and storing parity data in background memory during idle states, the system prepares error-correction resources in advance without interfering with normal read/write operations, thus improving reliability while avoiding performance degradation and excessive memory usage during active operations.
2Reliability
If parallel error-correction parity calculations are performed, then data protection is improved, but sequential read performance deteriorates
Solution Approach 1:
The system performs error-correction parity calculations during idle periods before read operations occur. By pre-computing parity data and storing it in background memory during idle states, the system ensures that when sequential read operations occur, the error-correction data is already available, thus maintaining data protection reliability while avoiding performance degradation during actual read operations.
Solution Approach 2:
The patent implements periodic background processing where error-correction parity calculations are performed during idle periods rather than continuously or concurrently with data operations. This periodic execution during idle states allows the system to maintain data protection capabilities while keeping the performance impact minimal, as calculations occur only when the system is not under load.
3Reliability
If temporary memory is used for parallel parity calculations, then error-correction capability is improved, but memory resource usage increases
Solution Approach 1:
The patent pre-calculates error-correction parity data during idle periods and stores it in background memory before it is needed. This preliminary action eliminates the need for temporary memory allocation during active read/write operations, as the parity data is already prepared and stored. Consequently, error-correction capability is maintained while temporary memory usage is eliminated.
Solution Approach 2:
The system creates copies of parity data in background memory during idle periods. These pre-created copies are stored separately from the main data storage area, allowing error-correction operations to use the copied parity data without consuming additional temporary memory resources during active operations. This copying approach maintains error-correction capability while minimizing memory resource usage.
Data Source
AI summary
Aspects of the present disclosure configure a system component, such as memory sub-system controller, to defer performance of an error-correction parity calculation for a block of a memory components of the memory subsystem. In particular, a memory sub-system controller of some embodiments can defer (e.g., delay) performance of an error-correction parity calculation and can defer the error-correction parity calculation such that it is performed at a time when the memory sub-system satisfies an idle state condition.