Dynamic Memory Read Retry Voltage Sequencing for Latency and Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory subsystems suffer from reduced system performance due to inefficient read retry operations, which cannot send data to a host device while conducting read retries, leading to imbalanced performance and power consumption.
Innovation Solution
The memory subsystem dynamically selects a read retry voltage sequence and trim settings based on the likelihood of a read retry timeout, prioritizing speed when a timeout is likely and power efficiency when speed is a lower priority, thereby improving system performance by balancing read retry latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional read retry operations are used, then data can be re-read after initial read failure, but system performance deteriorates because the memory subsystem cannot send data to host device during read retry
Solution Approach 1:
The patent implements dynamic voltage sequence selection that adapts read retry behavior based on real-time conditions. The memory subsystem controller dynamically chooses between different voltage sequences (first sequence for speed, second sequence for power efficiency) based on whether a timeout is likely, making the system flexible rather than static in its read retry approach
Solution Approach 2:
The patent changes operational parameters by selecting different voltage sequences based on timeout likelihood. When timeout is unlikely, it uses a first voltage sequence optimized for speed; when timeout is likely, it uses a second voltage sequence optimized for power efficiency, thereby adjusting parameters to balance reliability and productivity
2Loss of time
If read retry operations prioritize speed, then read retry latency decreases, but power consumption increases
Solution Approach 1:
The system dynamically adjusts voltage sequence selection based on timeout likelihood predictions. When timeout is unlikely, it prioritizes speed with the first voltage sequence; when timeout is likely, it prioritizes power efficiency with the second voltage sequence, creating a dynamic balance between time loss and energy consumption
Solution Approach 2:
The patent changes voltage sequence parameters based on operational conditions. It switches between a first voltage sequence (faster but more power-consuming) and a second voltage sequence (slower but more power-efficient) by evaluating timeout likelihood, thereby optimizing the trade-off between read retry latency and power consumption
3Use of energy by moving object
If read retry operations prioritize power efficiency, then power consumption decreases, but read retry latency increases
Solution Approach 1:
The system dynamically selects voltage sequences based on timeout likelihood. When timeout is likely, it uses the second voltage sequence for power efficiency; when timeout is unlikely, it uses the first voltage sequence for speed, creating a dynamic adaptation that balances power consumption and latency based on real-time conditions
Solution Approach 2:
The patent adjusts operational parameters by selecting different voltage sequences. It changes from a first voltage sequence (fast, high power) to a second voltage sequence (slower, low power) based on timeout probability, thereby optimizing the parameter trade-off between power consumption and read retry latency
Data Source
AI summary
Methods, systems, and apparatuses include determining to apply a read retry operation to a portion of memory. The likelihood of a read retry timeout meeting a threshold is determined. A reverse trim setting is selected in response to determining the likelihood of the read retry timeout meets the threshold. The read retry operation is executed using the selected trim setting.