Memory Subsystem Initialization Staggering Peak Current
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Solution Overview
Problem
Existing memory sub-systems face challenges in managing peak current levels during the reset and initialization of multiple memory dies, leading to inefficient power consumption and potential peak current overlap due to process, temperature, and voltage shifts, especially when individual CE control is used for each memory die.
Innovation Solution
Implementing a memory sub-system with a status register 'phase bit' for each memory die to indicate peak current phases, allowing a controller to stagger initialization commands and utilize a shared ready/busy output to identify safe phases for parallel execution without overlapping peak current events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory dies execute initialization phase simultaneously, then initialization speed is improved, but peak current consumption exceeds requirements
Solution Approach 1:
The patent implements periodic action by dividing the initialization process into distinct phases (charge pump initialization, word line ramp up, bit line charges) and sequentially activating memory dies across different phases rather than simultaneously. This periodic activation pattern ensures that peak current events from different dies do not overlap, maintaining power consumption within requirements while still achieving parallel initialization across multiple dies.
Solution Approach 2:
The patent applies preliminary action by implementing a readiness determination step before initiating initialization of each memory die. The controller checks whether a memory die is ready to begin initialization and only proceeds when conditions are appropriate. This preliminary check prevents simultaneous peak current events by ensuring dies are staggered into initialization at appropriate intervals, resolving the contradiction between speed and power consumption.
2Adaptability or versatility
If individual CE control is used for each memory die, then control flexibility is improved, but peak current overlap cannot be prevented due to process, temperature, and voltage shifts
Solution Approach 1:
The patent implements feedback by continuously monitoring the initialization state of each memory die and using this information to dynamically adjust when to initiate initialization of other dies. The controller determines readiness of each die based on its current phase and adjusts the timing of initialization commands accordingly. This feedback mechanism maintains control flexibility while reliably preventing peak current overlap despite process, temperature, and voltage variations.
Solution Approach 2:
The patent applies dynamics by making the initialization control adaptive rather than static. Instead of fixed timing for initializing each die, the system dynamically determines readiness based on actual die state, temperature, voltage conditions, and process variations. This dynamic approach preserves the flexibility of individual CE control while ensuring reliable prevention of peak current overlap through real-time adjustments.
Data Source
AI summary
A system to send a first command to execute an initialization process on a first memory die of a plurality of memory dies of a memory sub-system. The system reads a bit value indicating that the first memory die is executing a low peak current draw phase of the initialization process. In response to reading the bit value, sending a second command to a second memory die of the plurality of memory dies of the memory sub-system, the second command to execute the initialization process on the second memory die.