Memory Subsystem Architecture with Interleaved Data Clusters
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Solution Overview
Problem
Standardized memory modules optimized for low-end systems are inefficient when used in larger systems, leading to potential losses in efficiency and increased costs due to the need for custom designs to meet different system requirements.
Innovation Solution
A high-capacity memory subsystem architecture utilizing multiple memory modules arranged in clusters, each attached to a hub, which communicates with memory controllers at a higher bus frequency, allowing data to be distributed among multiple modules while maintaining the composite data rate, and enabling operation in both full and reduced bus frequency modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standardized memory modules are used in larger systems, then cost is reduced and manufacturing is simplified, but system performance and efficiency are lost
Solution Approach 1:
The memory system is segmented into multiple standardized memory modules organized in clusters, each cluster managed by a hub. This segmentation allows standardized modules to be combined in larger systems while maintaining performance through parallel access to multiple modules simultaneously.
Solution Approach 2:
The architecture employs a nested structure where standardized memory modules are nested within clusters, which are in turn nested within the larger memory system managed by hubs and controllers. This nesting enables standardized components to function effectively at multiple system scales.
2Quantity of substance
If memory capacity is increased to meet larger system requirements, then system capabilities are improved, but custom designs and increased costs are required
Solution Approach 1:
The hub and cluster architecture provides a universal interface that can accommodate any number of standardized memory modules. This universal design allows the same standardized modules to be used across different system configurations and capacities without requiring custom designs, achieving high memory capacity through simple replication of standard units.
3Use of energy by moving object
If bus frequency is reduced to lower power consumption, then energy efficiency is improved, but data transfer rate decreases
Solution Approach 1:
The system maintains continuous high data transfer rates by implementing parallel data paths through multiple memory modules and hubs. While individual bus operations may occur at lower frequencies to reduce power consumption, the aggregate data transfer rate remains high because multiple modules operate simultaneously, ensuring continuous useful action without sacrificing overall performance.
Data Source
AI summary
A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.