Memory Subsystem Internal Command Latency Reduction
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Solution Overview
Problem
Traditional memory access operations in memory sub-systems, such as NAND flash memory, face latency issues due to the distance between the command queue and the processor, leading to increased access times.
Innovation Solution
Implementing internal commands that allow a first processing core to generate and issue access operations independently of a reference queue, with a second core populating the queue, thereby reducing latency by signaling information directly for access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional command queue architecture is used where the processor accesses the reference queue for command information, then the system maintains a standardized command processing flow, but the access latency increases due to the physical distance between the command queue and processor
Solution Approach 1:
The command queue is divided into two separate components: a reference queue that stores command information and an internal command mechanism that allows direct processor access. This segmentation enables the processor to access critical command data without traversing the entire queue structure, reducing latency while maintaining the overall queue architecture for command management.
Solution Approach 2:
An internal command mechanism acts as an intermediary between the reference queue and the processor. This intermediary allows the processor to efficiently retrieve command information directly from the reference queue without the overhead of traditional queue access protocols, thereby reducing access latency while preserving the standardized command processing flow.
2Productivity
If the processor accesses the reference queue for every access operation, then command processing follows a consistent standardized flow, but the processing speed decreases due to repeated queue access overhead
Solution Approach 1:
Command information is pre-loaded into the reference queue in advance, allowing the processor to access previously prepared command data without real-time queue traversal. This preliminary preparation of command information in the reference queue enables faster processor access and improves overall processing speed while maintaining standardized command flow.
Solution Approach 2:
The internal command mechanism creates a copy or reference to command information in the reference queue that can be accessed directly by the processor. This copying approach allows the processor to retrieve command data without the overhead of full queue access protocols, thereby increasing processing speed while preserving the original command queue structure for maintaining standardized processing flows.
Data Source
AI summary
Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.