Memory Sub-System Command Processing via L2P Tracking

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Solution Overview

Problem

Conventional memory sub-systems face inefficiencies in processing commands, particularly when dealing with overlapping write and deallocate operations, leading to unnecessary data flushing and delays, which impact over-provisioning and processing time.

Innovation Solution

The memory sub-system employs an L2P tracking component to maintain the order of commands by tracking updates to the L2P mapping table, using the coherency table to determine the correct data to return for read commands, thereby avoiding unnecessary data flushing and allowing direct cache reads, and utilizing a flag to track the status of write commands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional memory sub-systems process write and deallocate commands in order, then command processing simplicity is maintained, but unnecessary data flushing and processing delays occur

Engineering Contradiction:
Improvecommand processing efficiencyVSAvoidprocessing delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system dynamically adjusts command processing based on L2P table update status. Write commands are processed differently depending on whether their L2P mapping is complete, allowing the system to switch between flushing data immediately or allowing direct cache reads, thereby optimizing processing efficiency and reducing unnecessary delays

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system uses L2P tracking components to monitor the status of write command processing and provides feedback to the command processing logic. This feedback mechanism enables the system to make informed decisions about whether to flush data or allow direct cache reads, resolving the contradiction between processing efficiency and timing accuracy

Inventive Principle:
Principle #23Feedback

2Reliability

If data is flushed to memory device immediately after write command, then data consistency is ensured, but over-provisioning is negatively impacted and processing time increases

Engineering Contradiction:
Improvedata consistencyVSAvoidsystem efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary tracking of L2P mapping updates before determining the final action. By monitoring whether the L2P table has been updated for a write command before deciding to flush or allow direct cache reads, the system ensures data consistency is maintained while avoiding unnecessary flushing operations that would reduce efficiency

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the processing parameter based on L2P update status. When L2P mapping is complete, the system allows direct cache reads; when incomplete, it flushes data. This parameter change approach maintains data consistency while optimizing system efficiency by avoiding unnecessary flushes

Inventive Principle:
Principle #35Parameter changes

3Stability of the object's composition

If L2P tracking component monitors all write commands, then command order is maintained, but system complexity increases

Engineering Contradiction:
Improvecommand orderVSAvoidtracking mechanism complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The system extracts only the critical tracking information (L2P mapping update status) from write commands rather than monitoring all aspects of command execution. This selective tracking approach maintains command order stability while minimizing the added complexity by focusing only on the essential status indicator

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11630778B2Efficient processing of commands in a memory sub-system
Publication Date: 2023.04.18 MICRON TECHNOLOGY INC
  • US11630778B2 patent drawing
  • US11630778B2 patent drawing
  • US11630778B2 patent drawing

AI summary

A write command is received, for example, from a host system, which operates on a first logical address range. A read command is received that specifies a second logical address range that matches the first logical address range. Responsive to determining that a deallocate command has been received after the write command, zero-filled data is returned in response to the read command.