Memory Subsystem Latency Control for Power Savings
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Solution Overview
Problem
Existing computer systems fail to effectively save power by monitoring the operating state of the memory subsystem independently of CPU/GPU or OS, and lack hardware-based solutions for power reduction without software intervention.
Innovation Solution
A computer system with a bus monitor connected to the system bus to track the frequency of CPU access requests to the memory subsystem, utilizing a latency changing mechanism to adjust access request latency based on the monitored load, thereby reducing power consumption by extending latency during low memory subsystem loads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the latency of access requests is reduced to improve processing speed, then system performance is improved, but power consumption increases
Solution Approach 1:
The memory subsystem dynamically adjusts latency based on real-time load conditions monitored by the bus monitor. When load is low, latency is increased to reduce power consumption; when load is high, latency is reduced to maintain performance. This dynamic adjustment resolves the contradiction by making the system adaptable to different operating conditions.
Solution Approach 2:
The invention changes the latency parameter of access requests based on monitored load conditions. By varying this temporal parameter according to system state, the invention achieves both power savings during low-load periods and performance maintenance during high-load periods, resolving the speed-power consumption contradiction.
2Use of energy by moving object
If the processing speed is reduced to save power, then power consumption decreases, but system performance deteriorates
Solution Approach 1:
The system dynamically adjusts processing speed through latency modification only when load conditions permit. The bus monitor continuously assesses load, and the memory subsystem adjusts latency accordingly, ensuring performance is maintained during high-load periods while achieving power savings during low-load periods.
Solution Approach 2:
The invention implements periodic monitoring of load conditions by the bus monitor and periodic adjustment of latency by the memory subsystem. This periodic action allows the system to alternate between power-saving mode and performance mode based on real-time conditions, resolving the contradiction between power consumption and performance.
3Use of energy by moving object
If latency is increased to reduce power consumption, then power savings are achieved, but access time increases
Solution Approach 1:
The invention changes the latency parameter dynamically based on load conditions. By monitoring load and adjusting latency accordingly, the system achieves power savings through increased latency only when load is low, while maintaining acceptable access times during high-load periods when performance is prioritized.
4Device complexity
If hardware-based power saving mechanisms are implemented without software intervention, then system complexity is reduced, but control precision may be compromised
Solution Approach 1:
The memory subsystem performs self-service by autonomously monitoring its own load conditions through the bus monitor and automatically adjusting its latency and power consumption accordingly. This self-service mechanism eliminates the need for external software intervention while maintaining precise control through direct hardware monitoring of access request frequencies.
Solution Approach 2:
The bus monitor provides continuous feedback on load conditions (access request frequencies) to the memory subsystem, which uses this feedback to adjust its operation. This feedback loop enables precise hardware-based control of power consumption and performance without requiring software intervention, resolving the contradiction between complexity and control precision.
Data Source
AI summary
A computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other, wherein the memory subsystem comprises a memory controller connected to the system bus, the computer system includes an up/down counter for counting a number of access requests and a number of requests other than access requests, a comparator for comparing the count of the up/down counter with a predetermined threshold value stored in a register, and a clock gate circuit for generating clock gate signals to decimate an operating clock of the memory controller in response to the comparison result of the comparator.