Memory Subsystem Mode Switching for ML Computation Routing
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Solution Overview
Problem
Conventional memory sub-systems lack a mechanism to determine which components commands and data are directed to, leading to errors when routing commands and data to multiple components, as they only handle memory components and not additional logic components for machine learning computations.
Innovation Solution
Implementing a memory sub-system with two operation modes: one for traditional data storage and retrieval, and another for machine learning computations, allowing the host system to access either memory cells or logic components through a single interface, using a mode managing component to configure the operation mode based on a mode setting signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a memory sub-system includes only memory components for data storage, then the system is simple and easy to operate, but it cannot perform machine learning computations and lacks versatility
Solution Approach 1:
The patent combines memory components and logic components into a single memory sub-system package, allowing both data storage and machine learning computations to be performed within the same device. This merging approach enables the system to handle both traditional memory operations and AI workloads without requiring separate systems.
Solution Approach 2:
The memory sub-system is designed to perform multiple functions: it can operate as a traditional memory device for data storage and retrieval, and simultaneously function as a processing unit for machine learning computations. The inclusion of both memory cells and logic components with a unified interface achieves multi-functionality.
2Adaptability or versatility
If the memory sub-system includes multiple components (memory and logic), then functionality is improved, but routing commands and data to the correct component becomes complex and error-prone
Solution Approach 1:
The interface circuitry is designed as a universal interface that can communicate with both memory components and logic components using the same protocol and signal lines. This unified interface eliminates the need for separate communication channels, simplifying command routing and reducing operational complexity despite the presence of multiple component types.
3Ease of operation
If separate interfaces are provided for memory components and logic components, then component access is simplified, but device complexity and implementation cost increase
Solution Approach 1:
The patent implements a single universal interface that serves both memory and logic components, eliminating the need for separate interfaces. This approach reduces device complexity and implementation cost while maintaining ease of access to both component types through the same communication channel.
4Reliability
If conventional memory sub-systems handle only memory operations, then the system is reliable for storage tasks, but it cannot accurately route commands for machine learning computations
Solution Approach 1:
The memory sub-system dynamically adapts its operation mode based on the received commands. The system can switch between memory access operations and logic computation operations depending on the command type, ensuring reliable and accurate routing to the appropriate component for each specific task while supporting multiple operation types.
Data Source
AI summary
A system can include a memory device with an array of memory cells and a machine learning operation component. The machine learning operation component can perform a machine learning computation in association with the array of memory cells. The system can also include a processing device that is operatively coupled with the memory device to perform operations that include setting the memory device to a first mode based on a first mode setting signal received from a host system, where in the first mode, the processing device exposes the array of memory cells to the host system and routes input data from the host system to the array of memory cells. The operations can also include, setting the memory device to a second mode, where in the second mode, the processing device exposes the machine learning operation component to the host system.