Memory Subsystem With Internal Modify Circuitry for Counter Updates
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Solution Overview
Problem
In network analyzer devices with a large number of counters, the cost and die-area for on-chip storage become prohibitive, and standard DRAM devices require high I/O bandwidth and power to support line-rate updates, leading to long latency in counter modifications.
Innovation Solution
A memory device that performs Read-Modify-Write operations internally, reducing the need for data transfer to an external host device, thereby minimizing I/O bandwidth and power consumption by using embedded DRAM arrays and control circuits to generate signals for modifying data within the memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard DRAM devices are used to store counters, then the counters can be updated at line-rate, but the I/O bandwidth requirement increases significantly
Solution Approach 1:
The patent combines the counter storage memory with modify circuitry into a single integrated device. The memory array stores counter values while embedded modify circuits perform increment/decrement operations internally, merging storage and processing functions to reduce external I/O bandwidth requirements by keeping counter data within the memory device during modify operations
Solution Approach 2:
The patent introduces an intermediary modify circuit within the memory device that acts as a mediator between external hosts and counter data. Instead of transferring counter data to external devices for modification, the intermediary modify circuit performs operations internally, reducing the quantity of data that must traverse external I/O interfaces
2Productivity
If standard DRAM devices are used to store counters, then the counters can be updated at line-rate, but the power consumption increases to support the greater bandwidth
Solution Approach 1:
The patent combines the counter storage memory with modify circuitry into a single integrated device. The memory array stores counter values while embedded modify circuits perform increment/decrement operations internally, merging storage and processing functions to reduce external I/O bandwidth requirements by keeping counter data within the memory device during modify operations, thereby reducing power consumption associated with external data transfer
Solution Approach 2:
The patent introduces an intermediary modify circuit within the memory device that acts as a mediator between external hosts and counter data. Instead of transferring counter data to external devices for modification, the intermediary modify circuit performs operations internally, reducing the quantity of data that must traverse external I/O interfaces and the power required to support such transfers
3Productivity
If standard DRAM devices are used to store counters, then the counters can be updated at line-rate, but the read-modify-write latency increases due to exchanges between memory device and host device
Solution Approach 1:
The patent combines the counter storage memory with modify circuitry into a single integrated device. The memory array stores counter values while embedded modify circuits perform increment/decrement operations internally, eliminating the need to transfer counter data to external hosts for modification. This integration significantly reduces read-modify-write latency by performing operations within the memory device itself rather than through external exchanges
Solution Approach 2:
The patent introduces an intermediary modify circuit within the memory device that acts as a mediator between external hosts and counter data. Instead of transferring counter data to external devices for modification, the intermediary modify circuit performs operations internally, reducing the quantity of data that must traverse external I/O interfaces and the time required for such transfers
4Ease of operation
If on-chip storage is used for counters, then the counters are easily accessible, but the die-area becomes prohibitive when the number of counters is very large
Solution Approach 1:
The patent combines the counter storage memory with modify circuitry into a single integrated device, allowing large numbers of counters to be stored in memory arrays while maintaining easy accessibility through embedded control circuits that can perform operations internally without requiring external data transfer
Solution Approach 2:
The patent introduces control circuits as intermediaries between external hosts and the memory arrays storing counters. These intermediary control circuits enable efficient access and modification of counter data stored in memory, maintaining ease of operation while allowing large numbers of counters to be stored with reduced die-area overhead compared to traditional on-chip register-based counters
Data Source
AI summary
A memory device and related techniques are provided to modify data stored in the memory device without the need to send the data to an external device. A command is received at the memory device to modify data stored at a memory location in a memory array of the memory device. The command includes a value to be used for modifying the data. The memory device reads data from the memory location. The data read from the memory location is modified with modify circuit in the memory device based on the value obtained form the command to produce results data. The results data produced by the modify circuit is written back to the memory location. Since the memory device does not need to send the data read from the memory array off-chip to another device, referred to herein as a host device, to update the data, the input/output bandwidth of the bandwidth is substantially reduced, allowing for lower power memory device operation and reduced latency.