Memory Subsystem Power Loss Protection via Traffic Control

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Solution Overview

Problem

Conventional memory systems face data loss during power outages due to the inability to secure in-flight data in non-volatile memory devices, leading to potential corruption and performance degradation.

Innovation Solution

Implementing a power loss protection scheme within the memory sub-system that detects impending power loss, stops data traffic, and ensures completion of pending read/write operations using capacitors to maintain data integrity by prioritizing energy distribution to critical components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data traffic continues during power loss events, then throughput is maintained, but data integrity deteriorates due to potential corruption of in-flight data

Engineering Contradiction:
Improvedata integrityVSAvoidthroughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system detects impending power loss conditions and proactively stops data traffic before complete power loss occurs. This preliminary action allows in-flight data to be secured or aborted before corruption can happen, ensuring data integrity while maintaining normal throughput during non-critical conditions

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system applies a counter-action by stopping data traffic in response to detected power loss conditions. This anti-action prevents the harmful effect of data corruption by reversing the normal data flow operation when reliability becomes compromised

Inventive Principle:
Principle #9Preliminary anti-action

2Duration of action of moving object

If capacitors are used to maintain power during potential power loss, then operational time is extended, but energy consumption increases

Engineering Contradiction:
Improveoperational timeVSAvoidenergy consumption
Core Design Contradiction:
Duration of action of moving objectVSUse of energy by moving object

Solution Approach 1:

Instead of continuously charging capacitors at full capacity, the system applies partial action by only charging them when power loss conditions are detected. This reduces normal energy consumption while providing sufficient energy extension during critical moments when needed

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The capacitor charging operates periodically rather than continuously - charging occurs during normal operation cycles and discharges during detected power loss events. This periodic action extends operational time during crises while minimizing continuous energy drain during normal operation

Inventive Principle:
Principle #19Periodic action

3Reliability

If data traffic is stopped during power loss events, then data integrity is protected, but energy distribution efficiency decreases

Engineering Contradiction:
Improvedata integrityVSAvoidenergy distribution efficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The system applies local quality by selectively stopping data traffic only in the specific subsystems or channels affected by power loss conditions, rather than shutting down the entire system. This allows energy to be efficiently distributed to critical components while protecting data integrity in affected areas

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces energy consumption, extends operational time during power loss events, and ensures data integrity by securing in-flight data before complete power loss, enhancing the reliability and efficiency of memory devices.

Implementation Method 1

ensures completion of pending read/write operations using capacitors to maintain data integrity

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11747994B2Power loss protection of data in memory devices
Publication Date: 2023.09.05 MICRON TECHNOLOGY INC
  • US11747994B2 patent drawing
  • US11747994B2 patent drawing
  • US11747994B2 patent drawing

AI summary

A system can include multiple memory devices and a processing device that is operatively coupled with the memory devices as well as with a controller device, and a sequencer device, where the controller device is configured to perform operations. The operations can include, in response to receiving a potential power loss indication signal, receiving a power fault interrupt detection signal, as well as synchronizing the power fault interrupt detection signal. They can also include sending one or more memory access commands to the sequencer device. The operations can also include executing the one or more memory access commands on a medium and stopping transmission of commands based on a power loss handling setting while executing the commands.