Memory Subsystem Scrambling via Physical Block Address
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Solution Overview
Problem
Conventional memory sub-systems face issues with data distribution and cell wear due to deterministic pseudorandom number generators (PRNGs) that reuse specific data patterns, leading to program disturb and premature degradation of memory cells.
Innovation Solution
The memory sub-system performs scrambling operations based on the entire physical block address (PBA) using bitwise XOR operations to generate a seed value, which is then used to create a randomized sequence for data storage, distributing write data more uniformly across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If deterministic pseudorandom number generators are used for scrambling operations, then the scrambling process is simple and deterministic, but data patterns are reused leading to program disturb and premature degradation of memory cells
Solution Approach 1:
The patent changes the seed generation parameters by incorporating more address bits (expanding from 8 bits to potentially more bits of the physical block address) and modifying the bitwise XOR operation parameters. This increases the randomness of the scrambling sequence without significantly increasing system complexity, thereby preventing data pattern reuse and reducing program disturb while maintaining operational simplicity
Solution Approach 2:
The patent introduces dynamic seed generation based on the physical block address, making the scrambling sequence vary according to the address being accessed. This dynamic approach ensures that different blocks use different scrambling patterns, preventing repetitive data patterns and extending memory cell lifespan while keeping the mechanism relatively simple
2Ease of manufacture
If conventional scrambling operations are used, then the implementation is straightforward, but data is not uniformly distributed across memory cells causing overuse of specific cells
Solution Approach 1:
The patent modifies the scrambling parameters by using extended address bits and adjusted XOR operations to achieve more uniform data distribution across memory cells. This maintains implementation ease while significantly improving distribution uniformity, preventing overuse of specific cells
3Productivity
If deterministic PRNG is used for scrambling, then the process is computationally efficient, but randomness is insufficient leading to repetitive data patterns
Solution Approach 1:
The patent enhances randomness by changing the seed generation parameters to include more address bits and modifying the XOR operation parameters. This maintains computational efficiency while significantly improving data pattern randomness, preventing repetitive patterns and extending memory device lifespan
Data Source
AI summary
Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving a write data request to store write data to the memory device; determining a physical block address associated with the write data request; performing a bitwise operation on each bit of the physical block address to generate a seed value; generating an output sequence based on the seed value; performing another bitwise operation on the output sequence and the write data to generate a randomized sequence; and storing, on the memory device, the randomized sequence.