Memory Subsystem Test Resource Power and Data Transmission
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Solution Overview
Problem
Conventional memory device testing systems are inefficient due to the need for sequential temperature and condition testing, which increases testing time and latency, and often require multiple signals to be transmitted through customer interface ports, leading to higher latency and reduced testing robustness.
Innovation Solution
A distributed memory device test platform with multiple test resources, each equipped with a processing device, test condition components, and dual interface ports (non-serial and serial IO) to transmit power and instructions simultaneously, allowing for concurrent testing of multiple conditions and operations across multiple memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If sequential temperature and condition testing is performed in a single chamber, then testing can be completed with simple equipment, but testing time and latency increase significantly
Solution Approach 1:
The test platform is divided into multiple independent test chambers (first chamber, second chamber, third chamber), each capable of performing tests independently. This segmentation allows concurrent testing of multiple memory devices under different temperature conditions, dramatically reducing total testing time while distributing the complexity across modular units.
Solution Approach 2:
The system transitions from sequential single-chamber testing to parallel multi-chamber testing, adding a spatial dimension to the testing process. Multiple chambers operate simultaneously at different temperature levels, transforming a time-sequential process into a space-parallel process that reduces overall testing time.
2Reliability
If multiple signals are transmitted through customer interface ports for testing, then comprehensive testing can be performed, but latency increases due to signal transmission overhead
Solution Approach 1:
The system extracts and separates the power transmission function from the data signaling function. A dedicated power supply signal is transmitted through the customer interface port to provide power to the memory device, while test instructions and data are transmitted separately through a serial IO port. This extraction eliminates the need for multiple complex signals to share the same interface, reducing latency while maintaining comprehensive testing capability.
Solution Approach 2:
The customer interface port is given multiple functions: it serves both as a data communication interface and as a power supply interface. By making the interface universal, the system reduces the number of separate connections needed, thereby reducing latency and signal transmission overhead while maintaining comprehensive testing robustness.
3Productivity
If a single chamber tests multiple memory devices at one temperature at a time, then equipment simplicity is maintained, but testing efficiency decreases
Solution Approach 1:
The testing system is segmented into multiple independent chambers, each capable of testing memory devices independently at different temperature conditions. This allows parallel testing operations across multiple chambers, significantly improving productivity while distributing the complexity across modular, manageable units.
Solution Approach 2:
Each test chamber is configured to operate at different temperature parameters (first temperature, second temperature, third temperature). By changing the temperature parameter across multiple chambers, the system enables concurrent testing under various thermal conditions, improving productivity without requiring a single overly complex chamber.
Data Source
AI summary
A processing device of a memory device test resource detects that a memory sub-system has engaged with a first memory sub-system interface port and a second memory sub-system interface port of the memory device test resource. The processing device causes a power supply signal to be transmitted from the memory device test resource to the memory sub-system via the first memory sub-system interface port. The processing device identifies a test to be performed for a memory device of the memory sub-system, where the test includes one or more test instructions to be executed in performance of the test. The processing device causes the one or more test instructions to be transmitted from the memory device test resource to the memory sub-system via the second memory sub-system interface port, where the test is performed by the one or more test instructions executing at the memory sub-system.