Memory Subsystem Threshold Voltage Offset Bin Selection
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Solution Overview
Problem
Existing memory sub-systems fail to adequately address the temporal voltage shift caused by slow charge loss in memory cells, leading to increased bit error rates during read operations.
Innovation Solution
The memory sub-system employs block family-based error avoidance strategies by tracking temporal voltage shifts and applying appropriate voltage offsets to base read levels for groups of memory cells programmed within specified time and temperature windows, using a block family manager component to associate blocks with threshold voltage offset bins for improved read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage offsets are applied to compensate for temporal voltage shift, then read accuracy is improved, but device complexity increases due to calibration operations and metadata management
Solution Approach 1:
The patent performs calibration operations in advance to determine optimal voltage offsets for different block families. These calibration results are stored as metadata and reused during subsequent read operations, avoiding the need to perform complex calibration measurements during every read operation. This preliminary action approach maintains high read accuracy while reducing operational complexity.
Solution Approach 2:
The patent creates simplified representations of voltage distribution characteristics through metadata that captures essential parameters of block families. Instead of performing full calibration analysis during each read operation, the system uses these pre-computed metadata copies to quickly determine appropriate voltage offsets, significantly reducing computational complexity while maintaining measurement precision.
2Reliability
If block family-based calibration is performed, then bit error rate is reduced, but manufacturing complexity increases due to additional metadata structures and calibration processes
Solution Approach 1:
The patent divides the memory device into block families based on temporal characteristics of charge loss. By segmenting the memory space into groups with similar voltage drift behavior, the system can apply targeted calibration strategies to each segment rather than treating all blocks uniformly. This segmentation enables more efficient calibration processes and reduces the overall manufacturing complexity while improving reliability.
Solution Approach 2:
The patent changes the parameter used for calibration from individual block-level characteristics to block family-level temporal voltage shift characteristics. This parameter transformation allows the system to capture essential reliability information with fewer measurements and simpler metadata structures, reducing manufacturing complexity while maintaining or improving bit error rate performance through more robust statistical sampling across larger groups.
3Measurement precision
If threshold voltage offset bins are selected by package, then read operations are enhanced, but loss of time occurs during calibration and bin selection processes
Solution Approach 1:
The patent merges multiple dice within a package into shared block families when they exhibit similar temporal voltage shift characteristics. By combining calibration data across multiple dice and selecting a single threshold voltage offset bin for the entire package, the system performs calibration once per package rather than once per die. This merging approach maintains measurement precision for read operations while reducing calibration time by a factor proportional to the number of dice per package.
Data Source
AI summary
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to program a first block in a first die of the memory device and a second block in a second die of the memory device, wherein the first die and the second die are assigned to a die group; and associate the die group with a threshold voltage offset bin.