3D Memory Device Sub-Test Circuit for Bonding Overlay Failure Detection
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Solution Overview
Problem
As the degree of integration in memory devices increases, failures due to various causes also rise, particularly bonding overlay failures which are difficult to detect effectively in three-dimensional memory devices.
Innovation Solution
A memory device comprising a first chip with a memory cell array and a second chip overlapping with the first chip, featuring sub-test pads, sub-test circuits, and a detection circuit to output signals and determine alignment errors, allowing for the detection of bonding overlay failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of memory devices increases, then storage capacity and functionality are improved, but failures due to various causes generally increase
Solution Approach 1:
The patent implements preliminary testing actions by incorporating test circuits and test pads that enable bonding overlay failure detection before the memory device is fully operational. The test circuit applies test signals to bonding regions and detects alignment errors proactively, allowing failures to be identified and addressed before they affect normal device operation.
2Quantity of substance
If three-dimensional memory device structure is used to increase integration, then storage capacity is improved, but bonding overlay failures become more difficult to detect
Solution Approach 1:
The patent introduces an intermediary test circuit system that mediates between the bonding structure and the detection mechanism. The test circuit includes test pads positioned at specific locations and a detection circuit that serves as an intermediary to apply test signals and measure bonding overlay alignment, making the detection of bonding failures feasible in three-dimensional structures.
Solution Approach 2:
The patent replaces direct mechanical inspection methods with an electrical field-based detection system. Instead of physically examining bonding alignment, the test circuit uses electrical signals applied through test pads to detect alignment errors, substituting mechanical detection with electrical measurement that is more suitable for three-dimensional integrated structures.
3Quantity of substance
If multiple chips are bonded together in three-dimensional structure, then storage capacity is improved, but alignment errors between chips increase
Solution Approach 1:
The patent implements a feedback mechanism where the detection circuit measures alignment errors between bonded chips and provides information that can be used to adjust or compensate for misalignment. The test signal application and detection process creates a feedback loop that enables real-time or post-bonding assessment of alignment accuracy, allowing for correction or identification of precision issues.
Data Source
AI summary
A memory device, and a method of testing the memory device for failure, includes a first chip including a memory cell array and a second chip overlapping with the first chip. The second chip includes: a semiconductor substrate including a peripheral circuit area and a lower test area; a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other; a plurality of sub-test circuits respectively connected to the plurality of sub-test pads; and a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals.