Memory Subword Driver Circuits Reducing Gate Induced Drain Leakage
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Solution Overview
Problem
The increasing scaling down of array access devices in semiconductor fabrication leads to growing concerns about leak currents, particularly gate-induced drain leakage (GIDL), which exceeds the maximum current capacity of memory testers during stress testing.
Innovation Solution
The implementation of a configuration where the gates of common transistors coupling subword lines are raised from ground level to a higher voltage during stress tests, reducing the voltage difference between the gate and drain and thereby minimizing GIDL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If array access devices are scaled down to increase integration density, then device miniaturization is achieved, but gate-induced drain leakage current increases
Solution Approach 1:
The patent changes the voltage parameter of the gate terminal by coupling it to a higher voltage level (e.g., Vcc or Vcc-0.5V) instead of ground potential. This parameter change reduces the gate-drain voltage difference, thereby suppressing GIDL current in scaled-down devices while maintaining the benefits of device miniaturization
2Object-generated harmful factors
If GIDL current is reduced by modifying transistor configuration, then leak current is minimized, but device complexity increases
Solution Approach 1:
The patent makes the gate terminal of the common transistor serve multiple functions: it still provides the necessary control function for transistor operation, and simultaneously acts as a voltage reference point coupled to higher voltage levels to suppress GIDL. This multi-functionality reduces leak current without adding significant complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces GIDL in common transistors, thereby reducing the total device current during stress tests and preventing the maximum current limit of memory testers from being exceeded.
Implementation Method 1
there is growing concerns regarding leak currents related to submicron devices fabricated on a semiconductor substrate such as the gate induced drain leakage (GIDL)
Data Source
AI summary
Apparatuses including and methods for memory subword driver circuits with reduced gate induced drain leakage are described. An example apparatus includes a first subword line and a second subword line coupled to the first subword line by a first common transistor where, in response to a test mode signal, a voltage of each of the first and second subword lines is raised to a first voltage and a gate voltage of the first common transistor is raised to a second voltage. In another example apparatus first and second subword drivers are coupled to the first and second subword lines respectively, and a driver circuit is coupled to the first and second subword drivers. The driver circuit outputs a first high signal to cause the first and second subword lines to rise to the first voltage and the gate voltage of the first common transistor to rise to the second voltage.