Memory Device Suspend Command Management for Latency Reduction
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Solution Overview
Problem
In memory devices, particularly NAND flash memory, true erase operations are lengthy and can be interrupted by suspend commands, leading to significant delays and stress on memory structures, negatively impacting quality of service and performance.
Innovation Solution
The memory device tracks suspend commands during true erase operations and applies a negative offset to the erase voltage when a threshold is reached, allowing for early completion of the true erase sub-operation and reducing the ramping period, thereby minimizing stress on memory lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the memory device allows suspend commands to interrupt true erase operations, then the quality of service and responsiveness are improved, but the latency and performance degradation increase due to the lengthy ramping period
Solution Approach 1:
The patent applies preliminary action by tracking suspend commands during the ramping period and proactively determining when to terminate the true erase sub-operation. Instead of waiting for the full ramping period to complete, the system monitors incoming suspend commands and prepares to interrupt the operation at the optimal point, thereby reducing latency while maintaining quality of service.
Solution Approach 2:
The patent implements dynamics by making the true erase sub-operation duration variable rather than fixed. The system dynamically adjusts the operation length based on the timing and number of suspend commands received, terminating the sub-operation early when appropriate. This dynamic approach allows the system to balance between completing erase operations and responding to suspend commands, reducing overall latency.
2Reliability
If the memory device completes the full true erase sub-operation before handling suspend commands, then the erase operation reliability is improved, but the stress on memory structures increases due to repeated ramping
Solution Approach 1:
The patent converts the potential harm of incomplete erase operations into a benefit by strategically terminating true erase sub-operations. By monitoring suspend commands and intelligently deciding when to interrupt the operation, the system transforms what could be a reliability risk into a mechanism that reduces stress on memory structures. The selective termination prevents excessive ramping while maintaining sufficient erase effectiveness.
Solution Approach 2:
The patent applies parameter changes by modifying the operational parameters of the true erase sub-operation based on suspend command patterns. The system changes the duration and timing of ramping periods dynamically, adjusting these parameters to balance erase reliability with stress reduction. This allows the system to maintain adequate erase performance while minimizing harmful stress accumulation.
3Adaptability or versatility
If the memory device allows multiple suspend commands during true erase operations, then the adaptability and responsiveness are improved, but the performance degradation worsens due to frequent interruptions
Solution Approach 1:
The patent applies preliminary action by establishing a monitoring mechanism that tracks suspend commands during the ramping period before the true erase sub-operation completes. This preliminary tracking allows the system to make informed decisions about when to terminate operations, enabling responsive handling of multiple suspend commands while maintaining overall performance through intelligent timing.
Solution Approach 2:
The patent implements dynamics by creating a flexible, adaptive system that responds to varying numbers and timings of suspend commands. The true erase sub-operation duration becomes dynamic rather than fixed, allowing the system to adjust its behavior based on real-time command patterns. This dynamic approach maintains productivity by avoiding unnecessary full completions while preserving adaptability to handle multiple suspend commands effectively.
Data Source
AI summary
A memory device includes a memory array comprising memory cells and control logic operatively coupled with the memory array. The control logic causes, as part of a true erase sub-operation, an erase pulse to be applied to one or more sub-blocks of the memory array. The control logic tracks a number of suspend commands received from a processing device, including suspend commands received while memory cells of the one or more sub-blocks are being erased. The control logic causes, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation. The control logic, in response to the number of suspend commands satisfying a threshold criterion, alerts the processing device to terminate sending suspend commands.