Memory Control Circuit for Adaptive Suspend Interval Scheduling

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Solution Overview

Problem

The performance of rewritable non-volatile memory modules is affected by the frequency of suspend commands, which pause ongoing write or erase operations to prioritize read operations, and the length of the time interval between these commands impacts overall system efficiency.

Innovation Solution

A memory control method that dynamically adjusts the suspend interval between suspend commands based on the load level of the rewritable non-volatile memory module, distinguishing between light and heavy loads to optimize the timing of read operations and reduce latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the suspend command interval is shortened to prioritize read operations, then read latency is reduced, but write and erase operations are frequently interrupted causing longer completion times

Engineering Contradiction:
Improveread latencyVSAvoidwrite and erase operation completion time
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent applies dynamics by making the suspend command interval adjustable rather than fixed. The memory control device dynamically changes the interval between suspend commands based on the current operation status and load conditions. When write or erase operations are detected, the device extends the suspend command interval to prevent frequent interruptions, while under normal conditions it maintains a shorter interval to ensure low read latency. This dynamic adjustment resolves the contradiction by adapting the interval to system needs.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements parameter changes by modifying the suspend command interval parameter according to different operational states. The memory control device monitors whether write or erase operations are currently executing and adjusts the interval parameter accordingly - extending it during intensive operations to reduce interruptions, and shortening it during idle periods to improve read responsiveness. This parameter adaptation directly addresses the technical contradiction.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the suspend command interval is lengthened to protect write and erase operations from frequent suspensions, then operation completion time is reduced, but read operation latency increases

Engineering Contradiction:
Improvewrite and erase operation completion timeVSAvoidread latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent resolves this contradiction through dynamic adjustment of the suspend command interval. When the memory control device detects that write or erase operations are in progress, it automatically extends the interval to protect these operations from frequent suspensions, thereby improving completion time. When no intensive operations are detected, the device shortens the interval to maintain low read latency. This dynamic behavior allows the system to optimize for different operational priorities at different times.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies preliminary action by proactively extending the suspend command interval before frequent suspensions can occur. The memory control device monitors the current operation status and preemptively adjusts the interval parameter to prevent the harmful effect of frequent suspensions on write and erase operations, rather than reacting after the problem occurs. This anticipatory adjustment maintains operation completion efficiency while preserving read responsiveness.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20260044282A1Memory control method, memory storage device, and memory control circuit unit
Publication Date: 2026.02.12 PHISON ELECTRONICS
  • US20260044282A1 patent drawing
  • US20260044282A1 patent drawing
  • US20260044282A1 patent drawing

AI summary

A memory control method, a memory storage device, and a memory control circuit unit for a rewritable non-volatile memory module are provided. The method includes: judging a load level of the rewritable non-volatile memory module; determining a suspend interval between a plurality of suspend commands according to the load level; and sequentially issuing the suspend commands to the rewritable non-volatile memory module according to the suspend interval. The suspend commands are configured to suspend an operation currently executed by the rewritable non-volatile memory module to execute a read operation. A time interval from an end of the read operation to receiving a next suspend command is greater than or equal to the suspend interval.