Memory Device Suspend and Resume Timing Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face inefficiencies in suspend and resume operations, particularly in NAND flash memory, due to unpredictable latency and overhead in implementing suspend and resume commands, which can disrupt priority operations like read and program operations.
Innovation Solution
The implementation of timing diagrams and flowcharts that outline specific control signals and operations for suspending and resuming program and erase operations within memory devices, allowing for automatic or command-driven suspension and resumption of operations without the need for explicit suspend and resume commands, thereby reducing latency and improving operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If explicit suspend and resume commands are used to manage memory operations, then operational control is improved, but latency and overhead increase
Solution Approach 1:
The patent extracts the suspend and resume functionality from explicit command sequences and integrates it into the timing structure of existing read and program operations. By removing the need for separate suspend/resume commands and embedding the functionality within operation timing diagrams, the patent reduces command overhead and latency while maintaining operational control.
Solution Approach 2:
The patent performs preliminary actions by pre-configuring timing parameters and operation sequences that automatically handle suspension and resumption. The timing diagrams are designed in advance to include suspension points and resumption protocols, eliminating the need for real-time command processing and reducing latency.
2Adaptability or versatility
If suspend and resume commands are implemented in NAND flash memory, then operational flexibility is improved, but device complexity increases
Solution Approach 1:
The patent makes the timing control mechanism universal by designing it to handle multiple operation types (read, program, erase) with a single integrated timing framework. The same timing diagram structure and control logic are applied across different operation modes, eliminating the need for separate complex control circuits for each operation type and reducing overall device complexity.
3Adaptability or versatility
If priority operations like read and program are interrupted for suspend/resume, then operational adaptability is improved, but productivity decreases
Solution Approach 1:
The patent implements periodic action by using fixed timing intervals and cyclical operation patterns in the timing diagrams. Operations are structured to naturally pause and resume at predetermined periodic points, allowing priority operations to be temporarily interrupted for suspend/resume while maintaining overall operational rhythm and efficiency. This periodic structure ensures that interruptions are minimized and occur at optimal points in the operation cycle.
Data Source
AI summary
Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation; and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.