Memory Program-Verify Suspend Control for Shorter Wait Time
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Solution Overview
Problem
Existing memory devices face delays and inefficiencies in program suspend-resume operations due to unsuitable suspend points, leading to threshold voltage downshift and misclassification of memory cells, which causes program voltage overshoot and read-window loss, especially in multi-level cell programming.
Innovation Solution
Introduce new suspend points within the program verify loop based on a trim value, allowing selective execution of program verify operations before suspend, thereby improving Vt tracking and reducing wait time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the memory device waits for all program verify operations to complete before suspending, then the Vt tracking accuracy is improved, but the wait time to suspend increases
Solution Approach 1:
The patent applies partial action by performing only a subset of program verify operations (based on trim value) before suspending, rather than completing all verify operations. This partial verification provides sufficient Vt tracking accuracy while significantly reducing the wait time to suspend, resolving the contradiction between tracking precision and suspension speed.
Solution Approach 2:
The patent changes the parameter of verify operation count dynamically based on trim value. By adjusting the number of verify operations performed before suspend according to the trim value parameter, the system optimizes the balance between Vt tracking accuracy and suspension response time for different memory cell conditions.
2Loss of time
If the memory device reduces the number of program verify operations before suspend, then the wait time to suspend decreases, but the Vt tracking accuracy deteriorates
Solution Approach 1:
The patent uses trim value as a dynamic parameter to adjust the number of verify operations. This parameter change allows the system to adapt the verification depth based on memory cell characteristics, achieving fast suspension while maintaining adequate Vt tracking through optimized parameter selection.
Solution Approach 2:
The patent implements partial verification by performing only the necessary number of verify operations (determined by trim value) rather than all possible operations. This partial action provides sufficient tracking accuracy for the application while minimizing suspension delay.
3Speed
If the memory device suspends too early in the program verify loop, then the responsiveness to suspend command improves, but the program voltage overshoot increases
Solution Approach 1:
The patent changes the suspend timing parameter based on trim value, allowing flexible adjustment of when to suspend within the verify loop. This parameter optimization enables the system to achieve fast responsiveness while preventing voltage overshoot by suspending at the appropriate point in the verify sequence.
Solution Approach 2:
The patent uses trim value as feedback from previous programming operations to determine the optimal suspend point. This feedback mechanism allows the system to learn from past performance and adjust suspend timing to achieve both responsiveness and voltage precision.
Data Source
AI summary
A memory device includes a memory array having a plurality of memory cells. Control logic operatively is coupled with the memory array. The control logic receives a suspend command while programming multiple data states to a set of the plurality of memory cells of the memory array. The control logic determines whether a trim value associated with a program suspend operation is less than a total number of program verify operations to be performed during a present program verify loop of a programming operation. The control logic, in response to the trim value being less than the total number of program verify operations, causing only a subset of the total number of program verify operations that correspond to the trim value to be performed before causing a program suspend operation to be performed on the set of plurality of memory cells.