Memory Suspend Operations Verify Phase Completion

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Solution Overview

Problem

Existing memory systems face inefficiencies when suspending write operations during verify phases, leading to increased processing resources usage and potential inaccuracies in programming pulses due to charge loss.

Innovation Solution

The memory system is configured to complete the verify phase before suspending a write operation, updating latches accordingly, and transferring SSPC data to volatile memory to enable high-priority read operations without resuming the write operation with an additional verify phase.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a write operation is suspended during a verify phase, then high-priority read operations can be performed, but the write operation duration increases and processing resources are consumed

Engineering Contradiction:
Improveability to handle high-priority read operationsVSAvoidwrite operation duration
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by completing the verify phase before suspending the write operation. This ensures that the memory system has up-to-date information about the programming status, allowing for more efficient resumption and reducing the overall suspended duration while still enabling high-priority read operations

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If a write operation is suspended mid-verify phase, then read operations can proceed, but charge loss occurs leading to inaccurate programming pulse determination

Engineering Contradiction:
Improveability to perform read operationsVSAvoidprogramming pulse accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent completes the verify phase before suspension, ensuring that all charge state measurements are finalized and latches are updated with accurate programming status information. This preliminary completion eliminates charge loss during suspension and maintains measurement precision for future programming pulses

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent updates latches with verify phase results before suspending the write operation, creating a protective buffer that preserves accurate programming status information. This beforehand update prevents charge loss from affecting the stored state information, cushioning against potential accuracy degradation

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Productivity

If verify phase is completed before suspension, then resource consumption is reduced, but the suspension decision complexity increases

Engineering Contradiction:
Improveprocessing resource efficiencyVSAvoidsuspension control logic
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a clear preliminary action sequence: complete verify phase, update latches, then suspend. This structured approach simplifies the control logic by establishing explicit checkpoints and state transitions, making the suspension decision process more manageable while improving resource efficiency

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250181492A1Techniques for suspend operations
Publication Date: 2025.06.05 MICRON TECHNOLOGY INC
  • US20250181492A1 patent drawing
  • US20250181492A1 patent drawing
  • US20250181492A1 patent drawing

AI summary

Methods, systems, and devices for suspend operations are described. A memory device may perform a write operation including one or more programming phases and one or more verify phases. The memory device may receive a read command while performing the write operation and determine whether the verify phase of the write operation is complete. The memory device may suspend a performance of the write operation in response to determining that the verify phase of the write operation is complete. The memory device may transmit first information for the write operation from a first latch to a volatile memory device in response to suspending the performance of the write operation. The memory device may perform a read operation associated with the read command in response to suspending the performance of the write operation and transferring the first information.