Memory Swap Operations Using Sensing Circuitry
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Solution Overview
Problem
Existing memory technologies require significant power and time to perform swap operations, as they often necessitate transferring data between memory arrays and processing resources via buses, which can be inefficient and power-intensive, especially when only a single swap operation can be performed at a time.
Innovation Solution
The proposed solution involves performing swap operations within the memory array using sensing circuitry, which allows for parallel execution of swap operations without transferring data via input/output lines, reducing the need for external processing resources and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If data is transferred between memory arrays and processing resources via buses to perform swap operations, then the swap operation can be completed, but power consumption increases and time is extended
Solution Approach 1:
The patent extracts the swap operation functionality from external processing resources and relocates it directly into the memory array using sensing circuitry. This eliminates the need to transfer data via buses for swap operations, thereby reducing power consumption while maintaining swap operation capability.
Solution Approach 2:
The sensing circuitry acts as an intermediary component within the memory array that enables swap operations to be performed locally. Instead of using external processors and buses, the sensing circuitry mediates the swap operation by directly manipulating data bits within the memory array, reducing power consumption and transfer time.
2Ease of manufacture
If data is transferred between memory arrays and processing resources via buses to perform swap operations, then the swap operation can be completed, but the time required increases
Solution Approach 1:
The patent extracts the swap operation functionality from external processing resources and relocates it directly into the memory array using sensing circuitry. This eliminates the need to transfer data via buses for swap operations, thereby reducing power consumption while maintaining swap operation capability.
Solution Approach 2:
The sensing circuitry is pre-configured within the memory array to perform swap operations locally. By having the capability prepared in advance within the memory array itself, data does not need to be transferred out and back for simple swap operations, significantly reducing the time required.
3Measurement precision
If single swap operations are performed sequentially through external processing resources, then accuracy is maintained, but productivity decreases
Solution Approach 1:
The patent segments the swap operation capability into individual sensing circuitry units distributed throughout the memory array. Each sensing circuitry can independently perform swap operations on its associated data bits, enabling multiple parallel swap operations across different segments of the memory array, thereby increasing throughput while maintaining accuracy.
Solution Approach 2:
The patent transitions from sequential swap operations in a single processing pipeline to parallel swap operations across multiple spatial locations within the memory array. By utilizing the spatial dimension of the memory array architecture, multiple swap operations can occur simultaneously at different locations, dramatically increasing productivity while maintaining the precision of individual operations.
Data Source
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AI summary
Examples of the present disclosure provide apparatuses and methods related to performing swap operations in a memory. An example apparatus might include a first group of memory cells coupled to a first sense line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second sense line and configured to store a second element. An example apparatus might also include a controller configured to cause the first element to be stored in the second group of memory cells and the second element to be stored in the first group of memory cells by controlling sensing circuitry to perform a number operations without transferring data via an input/output (I/O) line.