Memory Swapping via Host-Storage Queue Collaboration
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Solution Overview
Problem
Existing virtual memory systems face performance bottlenecks due to slow memory swapping operations, which affect the overall speed and efficiency of data processing systems.
Innovation Solution
A method and apparatus that involve a host device and storage device collaboration, where queue information is transmitted and processed to optimize memory swapping tasks, including address conversion and memory interleaving, to overlap page-out and page-in operations, thereby enhancing swapping speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory swapping operations are performed sequentially in conventional virtual memory systems, then the system can maintain simplicity in operation control, but the memory swapping speed becomes slow and affects overall data processing performance
Solution Approach 1:
The storage device performs preliminary actions by executing part of the memory swapping task (such as address conversion and data preparation) based on queue information received from the host device before the actual swap command is issued. This preliminary processing reduces the time required when the actual swapping operation needs to be executed, thereby increasing memory swapping speed without adding significant operational complexity.
2Productivity
If the storage device performs address conversion and memory interleaving scheduling, then memory swapping speed increases, but the device complexity increases
Solution Approach 1:
The memory swapping task is segmented into multiple independent operations: queue information reception, address conversion, memory interleaving scheduling, and actual data swapping. The storage device performs the address conversion and scheduling segments in advance based on queue information, while the host device handles the final execution. This segmentation allows the storage device to prepare data structures and conversions without blocking the host, increasing throughput while distributing complexity across multiple components.
Solution Approach 2:
Queue information acts as an intermediary mechanism between the host device and storage device. The host device sends queue information containing swapping task details to the storage device, which then performs preliminary processing (address conversion, interleaving scheduling) based on this information. This intermediary approach allows the storage device to optimize its internal operations without requiring complex real-time coordination with the host, thereby increasing productivity while managing device complexity through standardized information exchange.
3Speed
If page-out and page-in operations are performed in the same memory chip, then the system structure remains simple, but the swapping speed is limited by sequential access
Solution Approach 1:
The patent merges the page-out and page-in operations into a single coordinated process at the storage device level. By performing both operations simultaneously on different memory chips based on memory interleaving scheduling, the system achieves parallel processing without requiring separate control mechanisms for each operation. This merging approach increases memory access speed by utilizing multiple chips in parallel while managing complexity through unified control at the storage device.
Solution Approach 2:
The system transitions from single-chip sequential operations to multi-chip parallel operations by introducing a new dimension of spatial distribution. Memory interleaving scheduling distributes page-out and page-in operations across multiple memory chips, effectively moving from a one-dimensional sequential access model to a multi-dimensional parallel access model. This dimensional change increases memory access speed by utilizing the spatial distribution of multiple chips, while the complexity is managed through the storage device's scheduling capability rather than requiring complex per-chip control.
Data Source
AI summary
A memory swapping method and a data processing system using the same, the memory swapping method including receiving queue information for a memory swapping task from a host device; performing part of the memory swapping task in a storage device based on the queue information; receiving a command corresponding to the queue information from the host device after performing of the part of the memory swapping task is completed; and performing a remaining part of the memory swapping task according to the command by using a result of the part of the memory swapping task that had been previously performed.