Memory Array Switch Segmentation for Lower Capacitive Loading
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Solution Overview
Problem
Current memory systems face challenges in reducing capacitive loading, which affects operating speed and power consumption, especially in large-scale memory arrays where global lines are loaded with all memory cells simultaneously, leading to inefficiencies.
Innovation Solution
Incorporating switches that allow individual configuration of local lines to couple or decouple subsets of memory cells to global lines, reducing capacitive loading to only the selected subset, thereby improving operating speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all memory cells are simultaneously connected to global lines, then complete memory access is enabled, but capacitive loading increases leading to slower operation and higher power consumption
Solution Approach 1:
The patent divides the memory array into multiple banks, with each bank further divided into subsets of memory cells. Switches enable selective connection of only the required subset to global lines, segmenting the capacitive load into manageable portions that can be accessed independently, thereby maintaining fast operation while preserving complete memory access capability across all banks.
Solution Approach 2:
The patent introduces dynamically controllable switches that can be enabled or disabled based on access requirements. These switches allow the system to adaptively connect only the necessary memory cell subsets to global lines during each operation, dynamically adjusting the capacitive loading to match the actual access needs, thus optimizing operating speed for each specific access pattern.
2Adaptability or versatility
If all memory cells are simultaneously connected to global lines, then complete memory access is enabled, but power consumption increases due to charging/discharging of all connected capacitive loads
Solution Approach 1:
By segmenting the memory array into banks and subsets with individual switch control, the patent enables power-efficient selective access. Only the switches and memory cell subsets that are actually accessed during a given operation are activated and connected to global lines, while all other switches remain disabled, isolating their capacitive loads and eliminating unnecessary power consumption for unaccessed memory regions.
Solution Approach 2:
The patent implements partial action by connecting only the necessary subset of memory cells to global lines rather than all memory cells. This partial connection approach charges and discharges only the minimal required capacitive load for each access operation, significantly reducing power consumption compared to simultaneously driving all memory cells, while still providing full memory access capability through selective activation.
3Speed
If switches are added to enable selective connection, then capacitive loading is reduced, but device complexity increases
Solution Approach 1:
The patent organizes switches into a hierarchical structure corresponding to the segmented memory banks and subsets. Each switch is associated with a specific subset and controlled by dedicated control signals, creating a modular and systematic control architecture. This segmented organization makes the complexity manageable by breaking down the control logic into independent, repeatable units that can be implemented using standard memory control circuitry.
Solution Approach 2:
The patent designs the switch control mechanism to be universal across all memory banks, using the same control signal generation and switching logic for each bank. The switches and their control circuits serve multiple functions: enabling selective subset access, isolating capacitive loads, and providing scalable expansion capability. This multi-functional universal design reduces overall system complexity by reusing proven control architectures rather than requiring custom control logic for each switch.
Data Source
AI summary
Disclosed herein are related to a memory array. In one aspect, the memory array includes a first set of memory cells including a first subset of memory cells and a second subset of memory cells. In one aspect, the memory array includes a first switch including a first electrode connected to first electrodes of the first subset of memory cells, and a second electrode connected to a first global line. In one aspect, the memory array includes a second switch including a first electrode connected to first electrodes of the second subset of memory cells, and a second electrode connected to the first global line.