Memory Device Switch Circuit Optimizes Data Loading
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Solution Overview
Problem
Current memory systems face inefficiencies in data loading times due to conventional storage group configurations, which result in longer data transfer paths and reduced performance.
Innovation Solution
The memory device incorporates a switch circuit that alternately couples first and second storage groups to data lines, optimizing data transfer by dividing column addresses and using identical path lengths for both storage groups, thereby reducing loading times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional storage group configurations are used, then device complexity is reduced, but data loading time increases due to longer data transfer paths
Solution Approach 1:
The storage groups are divided into multiple segments (first storage group and second storage group), each with its own dedicated data transfer path. This segmentation allows parallel data loading operations, reducing the overall data loading time by eliminating sequential access bottlenecks.
Solution Approach 2:
The patent introduces a new dimensional aspect to the storage architecture by adding multiple data transfer paths (first data line and second data line) that operate in parallel. This dimensional expansion transforms the single-path sequential access model into a multi-path parallel access model, significantly reducing data loading time.
2Area of stationary object
If storage groups are arranged adjacent to page buffers, then area utilization is improved, but data transfer path length increases
Solution Approach 1:
The storage system is segmented into multiple storage groups with dedicated data transfer paths. This segmentation allows the data transfer paths to be optimized independently, enabling shorter effective path lengths for each segment while maintaining compact area utilization through the adjacent arrangement of storage groups to page buffers.
Data Source
AI summary
The present disclosure relates to a memory device and a memory system having the same. The memory device includes page buffers arranged in a first direction and a second direction perpendicular to the first direction, a first storage group and a second storage group arranged adjacent to the page buffers in the second direction, and a switch circuit arranged between the first storage group and the second storage group and selectively coupling the first storage group and the second storage group to data lines according to a number of page buffers and a number of first and second storage groups.