Memory Cell Testing via Switch Unit and Latch Isolation
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Solution Overview
Problem
Conventional memory testing methods involving ultraviolet light (UV) erase operations are time-consuming and increase manufacturing costs, necessitating a reduction in the number of UV erase operations.
Innovation Solution
A floating gate memory system with a switch unit that connects and disconnects memory cells from a latch unit, allowing for testing without programming the memory cells and minimizing UV erase operations, utilizing a semiconductor device with memory cells, latch units, and switch units to control current flow representing bit '0' or '1' values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If UV erase operations are performed on the memory during testing, then the memory can be reset to a known state, but the testing time increases significantly and productivity decreases
Solution Approach 1:
The patent extracts the essential testing function from the complete programming-erase cycle. By using the latch unit to capture and hold test results, the system separates the critical verification step from the time-consuming UV erase operation, allowing testing to be performed without requiring full memory erasure and reprogramming
Solution Approach 2:
The latch unit performs preliminary capture of test results before any erase operation is needed. By pre-capturing the memory state information in the latch, the system prepares the necessary data in advance, eliminating the need to re-program memory after erasure for the purpose of re-testing
2Reliability
If multiple UV erase operations are performed during memory testing, then comprehensive memory verification is achieved, but manufacturing costs increase
Solution Approach 1:
The patent extracts the verification function from the costly UV erase cycle. By using the latch unit to preserve test results and the switch unit to control memory cell access, the system achieves comprehensive verification without requiring multiple expensive erase operations, reducing manufacturing costs while maintaining verification completeness
Data Source
AI summary
A memory includes a first memory cell, a second memory cell, a latch unit, and a switch unit. The latch unit has a true node and a complement node. The switch unit is responsive to a first control signal and a second control signal, and is configured to connect the first memory cell to the true node and to disconnect the second memory cell from the complement node in response to the first control signal and to connect the second memory cell to the complement node and to disconnect the first memory cell from the true node in response to the second control signal. A semiconductor device that includes the memory is also disclosed. A method for testing the memory is also disclosed.