Memory Array Switch Segmentation for Lower Global Line Loading
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Solution Overview
Problem
Memory systems face challenges in reducing capacitive loading, which affects operating speed and power consumption, especially in large-scale memory arrays where global lines are loaded with all memory cells simultaneously, leading to inefficiencies.
Innovation Solution
Incorporating switches that allow individual coupling or decoupling of local lines to global lines, enabling selective coupling of subsets of memory cells to global lines, thereby reducing capacitive loading to only the actively used subset, and sharing drivers to minimize area and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all memory cells are simultaneously connected to global lines, then the memory system can access any memory cell, but the capacitive loading on global lines increases significantly
Solution Approach 1:
The patent divides the memory array into multiple subsets, with each subset having its own local bit lines and local select lines. Switches are introduced to selectively connect these local lines to global lines, allowing the system to access only the required subset of memory cells at any given time. This segmentation reduces the capacitive loading on global lines from all memory cells to only the actively accessed subset.
Solution Approach 2:
The patent employs dynamically controllable switches that can be enabled or disabled based on the access pattern. These switches allow the memory system to adaptively reconfigure the connection between local and global lines, dynamically adjusting the capacitive loading to match the actual access requirements rather than being statically connected to all memory cells.
2Use of energy by moving object
If switches are added to enable selective coupling of memory cell subsets, then capacitive loading is reduced, but device complexity increases
Solution Approach 1:
The switch network is segmented and distributed across the memory array, with each switch managing a specific local line connection. This distributed architecture avoids the complexity of a centralized switch matrix while achieving the same capacitive loading reduction. Each switch is a simple controllable element that manages a localized connection.
Solution Approach 2:
The switches serve multiple functions: they act as connection elements between local and global lines, serve as selection mechanisms for memory cell subsets, and function as capacitive loading control elements. This multi-functionality reduces the need for additional dedicated components, thereby managing device complexity.
3Area of stationary object
If drivers are shared across multiple switches, then area and power usage are minimized, but control complexity increases
Solution Approach 1:
Multiple switches that control the same local line are driven by a common driver circuit. This merging of driver resources reduces the total number of driver circuits required, thereby minimizing the area occupied by driver electronics and reducing overall power consumption. The common driver efficiently controls multiple switches through shared control signals.
Solution Approach 2:
The control system prepares and issues coordinated control signals to multiple switches simultaneously through the shared driver. This preliminary coordination ensures that switches are enabled or disabled in the correct sequence and combination, managing the control complexity through pre-planned signal coordination rather than complex real-time control logic.
Data Source
AI summary
Disclosed herein are related to a memory array. In one aspect, the memory array includes a first set of memory cells including a first subset of memory cells and a second subset of memory cells. In one aspect, the memory array includes a first switch including a first electrode connected to first electrodes of the first subset of memory cells, and a second electrode connected to a first global line. In one aspect, the memory array includes a second switch including a first electrode connected to first electrodes of the second subset of memory cells, and a second electrode connected to the first global line.