Memory Switch Architecture for Signal Integrity
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Solution Overview
Problem
Conventional memory systems face challenges in increasing both operating speed and the number of memory chips connected to the same signal line without degrading signal integrity due to loading effects and RC delays.
Innovation Solution
The proposed memory system employs a printed circuit board with N memory semiconductor packages, a first switch, and a controller, where N signal lines connect the packages to the switch in an N-to-1 correspondence, and bi-directional buffers are used to connect the signal lines to the switch, allowing for increased chip connectivity without degrading signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating speed is increased by increasing frequency, then the data throughput is improved, but the input capacitance increases causing RC delay and degrading signal integrity
Solution Approach 1:
A switch is introduced as an intermediary component between the memory chips and the controller. This switch acts as a mediator that selectively connects individual memory chips to the controller through a single shared signal line, thereby eliminating the direct RC delay problem that occurs when multiple chips are connected in parallel to the same signal line at high frequencies
2Quantity of substance
If the total number of memory chips connected to the same signal line is increased to increase storage capacity, then the storage capacity is improved, but the load on the system increases causing RC delay and degrading signal integrity
Solution Approach 1:
The system segments the connection between memory chips and the controller by introducing a switch that can selectively connect individual chips. Instead of having all N chips connected simultaneously to the controller through N parallel signal lines, the switch enables time-division multiplexing where each chip is connected individually through a single shared signal line, thereby reducing the capacitive load on any single connection while maintaining the ability to access all N chips
Solution Approach 2:
A single signal line is designed to serve multiple functions by being shared among N different memory chips through the switch. This universal signal line can connect to any of the N chips sequentially, replacing the need for N separate dedicated signal lines, thereby reducing the overall system complexity and improving signal integrity while maintaining full access to all memory chips
Data Source
AI summary
A memory system having improved signal integrity includes a printed circuit board for use in a memory device, N memory semiconductor packages mounted on the printed circuit board, a first switch mounted on the printed circuit board, a controller mounted on the printed circuit board, N first signal lines connecting the semiconductor packages to the first switch such that the semiconductor packages and the first switch are in an N-to-1 correspondence, a second signal line connecting the first switch to the controller, and N selection lines connecting the semiconductor packages to the first switch such that the semiconductor packages and the first switch are in an N-to-1 correspondence. The N selection lines connect the semiconductor packages to the controller and transmit an enable signal. N is a natural number.