Memory Cell Switch Circuit Layout for Smaller Source Drivers
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Solution Overview
Problem
As semiconductor devices miniaturize, the reduced power supply voltage in logic circuits limits current flow through transistors, necessitating increased transistor area to maintain high breakdown voltage, which in turn expands the source driver circuit area, hindering chip size reduction in nonvolatile memory devices.
Innovation Solution
The semiconductor device employs a first switch with a second transistor configuration similar to the memory cell's transistors, allowing for reduced area occupation while maintaining high dielectric strength, and separates voltage control for the word and coupling gates to prevent dielectric breakdown and ensure proper operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the transistor area is increased to maintain sufficient current flow with high breakdown voltage, then the current flow capability is improved, but the chip area increases
Solution Approach 1:
The source driver circuit is segmented into multiple independent transistor units that can be selectively activated. Instead of using one large transistor, the circuit uses several smaller transistors (e.g., four transistors in parallel) to collectively provide the required current flow capability while maintaining high breakdown voltage. This segmentation allows the circuit to achieve the same power handling capacity with reduced individual transistor areas and better overall layout efficiency.
Solution Approach 2:
The patent employs a nested structure where control circuits are integrated within or adjacent to the transistor units they control. The control circuit for managing the segmented transistors is compactly arranged, with control lines routed through shared pathways. This nesting approach reduces the overall chip area by eliminating redundant control structures and optimizing the spatial relationship between control and execution elements.
2Power
If the transistor area is increased to ensure sufficient current flow, then the current flow capability is improved, but the source driver circuit area increases
Solution Approach 1:
The patent merges multiple control functions into a single integrated control circuit that manages the segmented transistors. Instead of having separate control circuits for each transistor, a unified control structure is implemented that can selectively activate and coordinate multiple transistor units. This merging reduces the total control circuit area while maintaining the ability to provide sufficient current flow through the combined transistor array.
Solution Approach 2:
The control circuit is designed with multi-functionality, capable of managing different numbers and configurations of transistor units depending on operational requirements. The same control structure can adapt to various current flow demands by selectively enabling appropriate subsets of the segmented transistors, eliminating the need for multiple dedicated control circuits for different operating modes.
3Power
If the gate width is increased to flow sufficient current with limited gate voltage, then the current flow capability is improved, but the occupied area increases
Solution Approach 1:
Instead of using one transistor with a large gate width, the patent segments the current path into multiple transistors with smaller individual gate widths. These segmented transistors are arranged in parallel configurations where their combined current capacity equals or exceeds that of a single large transistor, while the total occupied area is reduced due to more efficient packing and shared control structures.
Solution Approach 2:
The patent transitions from a single-dimensional approach (one large transistor) to a multi-dimensional arrangement by organizing multiple smaller transistors in parallel pathways. This dimensional change allows the current flow capability to be distributed across multiple channels, achieving the same total current capacity with reduced individual device dimensions and optimized overall layout.
Data Source
AI summary
An occupied area of the switch circuit electrically connected to a memory cell is reduced to reduce the size of a semiconductor device. A semiconductor device according to an embodiment includes a memory cell on a semiconductor substrate and a semiconductor chip in which a switch circuit electrically connected to the memory cell is formed, wherein the switch circuit includes a second transistor electrically connected to the memory cell, and the second transistor includes a second word gate formed on the semiconductor substrate through a third gate insulating film, and a second coupling gate formed on the semiconductor substrate through a fourth gate insulating film having a thickness greater than that of the third gate insulating film, wherein a voltage higher than a voltage applied to the second word gate is applied to the second coupling gate of the second transistor when a current is applied to the memory cell.