Semiconductor Memory Synchronization Circuit Using Delayed Resynchronization
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Solution Overview
Problem
Existing synchronization circuits face challenges in synchronizing data across different clock domains with a small circuit scale, often resulting in metastable states due to insufficient setup or hold margins.
Innovation Solution
A synchronization circuit comprising a first and second delay circuit to generate delayed synchronization signals, and resynchronization circuits to update output data when inconsistencies are detected between synchronized data and delayed data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronization circuit uses a data strobe signal to synchronize data across different clock domains, then the occurrence of metastable states is suppressed, but the circuit scale becomes large due to additional circuits
Solution Approach 1:
The synchronization circuit is divided into multiple independent synchronization circuits, each handling a portion of the data bits. This segmentation allows the use of simpler synchronization logic for each segment while maintaining overall reliability, thus reducing the total circuit scale compared to a single comprehensive synchronization circuit.
Solution Approach 2:
The patent uses multiple copies of the same synchronization circuit structure (first synchronization circuit, second synchronization circuit, third synchronization circuit) to handle different portions of data. This modular copying approach standardizes the design, reduces complexity through reuse, and maintains reliability through redundant synchronization paths.
2Speed
If the timing of input data is close to the timing of input clock, then data transfer speed is improved, but the setup margin or hold margin is not maintained causing metastable state
Solution Approach 1:
The synchronization circuit performs preliminary synchronization of input data with the clock signal before data transfer. By pre-aligning the data timing with the clock edges and providing multiple synchronization stages, the circuit ensures adequate setup and hold margins are met, preventing metastable states while enabling faster reliable data transfer.
Solution Approach 2:
The patent employs periodic clock signals with multiple phases to synchronize data at different timing points. This periodic synchronization approach allows the circuit to capture data at optimal moments, maintaining setup and hold margins while achieving high data transfer speeds through coordinated periodic sampling.
Data Source
AI summary
A synchronization circuit, a semiconductor storage device, and a synchronization method provided herein, which are capable of performing synchronization on a small circuit scale, includes: a first delay circuit delaying a input synchronization signal by a first predetermined time to generate a first delay synchronization signal; a second delay circuit delaying the first delay synchronization signal by a second predetermined time to generate a second delay synchronization signal; a first synchronization circuit outputting a first output data generated by synchronizing the input data with the input synchronization signal; a second synchronization circuit outputting a second output data generated by synchronizing the input data with the first delay synchronization signal; and a resynchronization circuit resynchronizing the input data with the second delay synchronization signal to update the first output data to the first synchronization circuit when the first output data is inconsistent with the second output data.