Memory System Address Operation Circuit for Cross-Point Array Disturbance
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Solution Overview
Problem
Next-generation memory devices face challenges in accessing multiple memory cells simultaneously without causing disturbance and heat-related data loss in cross-point array structures, particularly in resistive memory systems where cells closer to row and column circuits are more vulnerable to errors during read/write operations.
Innovation Solution
A memory system with multiple cell arrays and an address operation circuit that generates unique addresses for each cell array, allowing simultaneous access to memory cells at different positions across arrays, thereby reducing the likelihood of errors by avoiding simultaneous access to vulnerable cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory cells are accessed simultaneously in a cross-point array structure, then productivity is improved, but reliability deteriorates due to disturbance and heat-related data loss
Solution Approach 1:
The memory system divides the cross-point array into multiple cell arrays (first cell array, second cell array, etc.), each accessed independently with distinct addresses. This segmentation allows simultaneous access operations across arrays while isolating disturbance and heat effects to individual arrays, preventing cumulative errors that would occur with simultaneous access in a single array.
Solution Approach 2:
Different cell arrays are positioned at different locations in the memory device, creating local variations in thermal and disturbance characteristics. The address operation circuit generates unique addresses for each array, enabling the system to exploit these local quality differences to distribute access loads and avoid concentrating multiple accesses on vulnerable cells in the same location.
2Ease of operation
If cells closer to row and column circuits are accessed frequently, then ease of operation is improved, but object-affected harmful factors increase due to disturbance and heat
Solution Approach 1:
The patent extends the address space by adding a cell array identifier dimension to the traditional row-column addressing scheme. The address operation circuit generates addresses that include both the original row-column information and a cell array selector, enabling access to cells at different spatial positions across multiple arrays. This dimensional extension allows the system to distribute accesses away from vulnerable regions near row and column circuits to safer regions in other arrays.
3Productivity
If a single command accesses multiple memory cells, then productivity is improved, but device complexity increases due to address management requirements
Solution Approach 1:
The address operation circuit performs preliminary address transformation by adding cell array identifiers to base addresses before the addresses are used to access memory cells. This preliminary action of address modification enables the control logic to issue single commands for multi-cell access while the address operation circuit handles the complexity of generating distinct addresses for each target cell array, isolating the complexity from the control logic.
Data Source
AI summary
A memory system includes: a first cell array including a plurality of memory cells; and a second cell array including a plurality of memory cells; and an address operation circuit suitable for generating a first cell array address, the first cell array address used for accessing at least one first cell in the first cell array, by adding a first value to an address, and generating a second cell array address, the second cell array address used for accessing at least one second cell in the second cell array, by adding a second value to the address.