Memory System Logical-Physical Address Translation Wear Leveling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing memory systems using NAND-type flash memory face challenges in efficiently managing block units due to differences in data storage units between the host apparatus and nonvolatile semiconductor memory, leading to complex control requirements for wear leveling and bad block management.
Innovation Solution
A memory system with a nonvolatile semiconductor memory, cache memory, and a controller that uses parallel operation elements, management tables for address translation, and independent control units for updating these tables to manage physical and logical blocks, sectors, and addresses efficiently, thereby addressing wear leveling and bad block issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is directly recorded in an address designated from the outside, then data writing is simple, but erasing processing temporally concentrates in a specific area causing wear bias
Solution Approach 1:
The patent introduces a logical address layer as an intermediary between the host apparatus and the physical memory blocks. The logical-to-physical address translation mechanism acts as a mediator that decouples simple sequential writing from wear-aware block selection, allowing data to be written to logical addresses while the translation layer handles wear leveling to physical blocks
2Reliability
If wear leveling processing is performed by translating logical addresses to physical addresses, then wear is equally distributed, but control complexity increases due to address translation and block management
Solution Approach 1:
The patent segments the address space into logical addresses (simple sequential space) and physical addresses (wear-aware block space). This segmentation allows the system to maintain a simple interface for data writing while offloading wear leveling complexity to the translation layer that maps logical addresses to physically dispersed blocks
Solution Approach 2:
The logical-to-physical address translation mechanism serves as an intermediary that shields the host apparatus from wear leveling complexity. The translation layer handles block management, bad block avoidance, and wear distribution algorithms while presenting a simple sequential address space to the host
3Reliability
If bad blocks are avoided by accessing NAND flash memory with special handling, then data reliability is improved, but control complexity increases due to bad block management
Solution Approach 1:
The address translation layer acts as an intermediary that automatically handles bad block management. The translation mechanism queries block status, selects valid blocks for data storage, and updates the logical-to-physical mapping to avoid bad blocks, shielding the host apparatus from bad block complexity while ensuring data reliability
Data Source
AI summary
A memory system according to an embodiment of the present invention comprises: a data managing unit 120 is divided into a DRAM-layer managing unit 120a, a logical-NAND-layer managing unit 120b, and a physical-NAND-layer managing unit 120c to independently perform management of a DRAM layer, a logical NAND layer, and a physical NAND layer using the respective managing units to thereby perform efficient block management.